gem5 cache statistics - reset and dump

问题

I am trying to get familiar with gem5 simulator. To start, I wrote a simple program with

int main()
{
    m5_reset_stats(0, 0);
    m5_dump_stats(0, 0);
    return 0;
}

I compiled it with util/m5/m5op_x86.S and ran it using...

 ./build/X86/gem5.opt configs/example/se.py --caches -c ~/tmp/hello

The m5out/stats.txt shows (among other things)...

system.cpu.dcache.ReadReq_hits::total             881
system.cpu.dcache.WriteReq_hits::total            917
system.cpu.dcache.ReadReq_misses::total            54
system.cpu.dcache.WriteReq_misses::total           42

Why is an empty function showing so much hits and misses? Are the hits and misses caused by libc? If so, then what is the purpose of m5_reset_stats() and m5_dump_stats()?

回答1:

I would check in the stats.txt file if there are two chunks of

---Begin--- 
---End-----

because as you explained it, the simulator is supposed to dump the stats at dump_stats(0,0) and at the end of the run. So, it seems like you either are looking at one of those intervals (and I would expect the other interval to have 0 for all stats); or there was a bug in the simulation and the dump_stats() (or reset_stats())didn't actually do anything. That actually happened to me plenty of times, but I am not really sure as to the source of this bug.

If you want to troubleshoot further, you could do the following:

1. Look at the disassembly of your code and find the reset_stats.w and dump_stats.w
2. Dump a trace from gem5 and see if it ends up executing the dump and reset instructions and also what instructions (and how many) are executed before/after.

Hope this helps!

来源：https://stackoverflow.com/questions/23841867/gem5-cache-statistics-reset-and-dump