computer-architecture

问题 I am trying to get familiar with gem5 simulator. To start, I wrote a simple program with int main() { m5_reset_stats(0, 0); m5_dump_stats(0, 0); return 0; } I compiled it with util/m5/m5op_x86.S and ran it using... ./build/X86/gem5.opt configs/example/se.py --caches -c ~/tmp/hello The m5out/stats.txt shows (among other things)... system.cpu.dcache.ReadReq_hits::total 881 system.cpu.dcache.WriteReq_hits::total 917 system.cpu.dcache.ReadReq_misses::total 54 system.cpu.dcache.WriteReq_misses:

问题 Let's focus on uniprocessor computer systems. When a process gets created, as far as I know, the page table gets set up which maps the virtual addresses to the physical memory address space. Each process gets its own page table, stored in the kernel address space. But how does the MMU choose the right page table for the process since there is not only one process running and there will be many context switches happening? Any help is appreciated! Best, Simon 回答1: Processors have a privileged

问题 On MIPS architecture with pipelining and forwarding: add $s0, $t1, $t2 sw $s0, 0($sp) The add instruction will have the result ready at step 3 (execute operation) however I presume that the sw instruction want the result at step 2 (Instruction decode & register read). There is a solved exercise in the book Computer Organization and Design by David A. Patterson: Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls : lw $t1, 0($t0) lw $t2, 4(

问题 On MIPS architecture with pipelining and forwarding: add $s0, $t1, $t2 sw $s0, 0($sp) The add instruction will have the result ready at step 3 (execute operation) however I presume that the sw instruction want the result at step 2 (Instruction decode & register read). There is a solved exercise in the book Computer Organization and Design by David A. Patterson: Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls : lw $t1, 0($t0) lw $t2, 4(

问题 On MIPS architecture with pipelining and forwarding: add $s0, $t1, $t2 sw $s0, 0($sp) The add instruction will have the result ready at step 3 (execute operation) however I presume that the sw instruction want the result at step 2 (Instruction decode & register read). There is a solved exercise in the book Computer Organization and Design by David A. Patterson: Find the hazards in the following code segment and reorder the instructions to avoid any pipeline stalls : lw $t1, 0($t0) lw $t2, 4(

问题 i've recently learned about out-of-order execution CPUs in this link https://en.wikipedia.org/wiki/Out-of-order_execution There is something that i can't quite understand. Why aren't these kind of CPUs troublesome? I mean, if i have instructions executing out of order, even if they apply to different data, wont i be able to reach a situation where data is not updated according to the program order? I mean, if i have something like: x = 1; y = 2; x = x+y; print x; print y; what prevents the

问题 i've recently learned about out-of-order execution CPUs in this link https://en.wikipedia.org/wiki/Out-of-order_execution There is something that i can't quite understand. Why aren't these kind of CPUs troublesome? I mean, if i have instructions executing out of order, even if they apply to different data, wont i be able to reach a situation where data is not updated according to the program order? I mean, if i have something like: x = 1; y = 2; x = x+y; print x; print y; what prevents the

问题 i've recently learned about out-of-order execution CPUs in this link https://en.wikipedia.org/wiki/Out-of-order_execution There is something that i can't quite understand. Why aren't these kind of CPUs troublesome? I mean, if i have instructions executing out of order, even if they apply to different data, wont i be able to reach a situation where data is not updated according to the program order? I mean, if i have something like: x = 1; y = 2; x = x+y; print x; print y; what prevents the

来源： https://stackoverflow.com/questions/26955200/why-does-jmpq-of-x86-64-only-need-32-bit-length-address

问题 How system memory (RAM) is mapped for GPU access? I am clear about how virtual memory works for cpu but am not sure how would that work when GPU accesses GPU-mapped system memory (host). Basically something related to how Data is copied from system-memory to host-memory and vice versa. Can you provide explanations backed by reference articles please? 回答1: I found the following slideset quite useful: http://developer.amd.com/afds/assets/presentations/1004_final.pdf MEMORY SYSTEM ON FUSION APUS