gem5

问题 This is an important non-trivial question that comes up from time to time, so I would like to centralize its discussion. If some point needs further discussion, let's ask about it specifically on a separate question. Related mailing list posts: https://www.mail-archive.com/gem5-users@gem5.org/msg17206.html https://www.mail-archive.com/gem5-users@gem5.org/msg17615.html 回答1: What you always have to think is: some software is running (e.g. Linux kernel), and it might be storing state in memory

问题 Is it possible to add a new architecture to gem5 library? If I can add, then what is the procedure to do so. And is there any documents which can help me. I just want to add POWER-PC architecture though it has power architecture in it. 回答1: I would just copy one of the better maintained existing ISAs (X86, ARM or RISCV seem to be the best maintained to me), mass find and replace old ISA to new ISA name in all files, and then start hacking it up to look like your ISA. Basic userland syscall

问题 I've been trying to extract physical address accessed by the application in order to analyze the row hits. In doing so, I followed this page with little variation due to version change. I fixed CacheConfig.py as: system.monitor2 = CommMonitor() system.monitor2.trace = MemTraceProbe(trace_file = "CT_mon2.trc.gz") system.monitor2.slave = system.l2.mem_side system.membus.slave = system.monitor2.master system.l2.cpu_side = system.tol2bus.master And ran a code: build/X86/gem5.opt --debug-flag

问题 I've been trying to extract physical address accessed by the application in order to analyze the row hits. In doing so, I followed this page with little variation due to version change. I fixed CacheConfig.py as: system.monitor2 = CommMonitor() system.monitor2.trace = MemTraceProbe(trace_file = "CT_mon2.trc.gz") system.monitor2.slave = system.l2.mem_side system.membus.slave = system.monitor2.master system.l2.cpu_side = system.tol2bus.master And ran a code: build/X86/gem5.opt --debug-flag

问题 I am trying to get familiar with gem5 simulator. To start, I wrote a simple program with int main() { m5_reset_stats(0, 0); m5_dump_stats(0, 0); return 0; } I compiled it with util/m5/m5op_x86.S and ran it using... ./build/X86/gem5.opt configs/example/se.py --caches -c ~/tmp/hello The m5out/stats.txt shows (among other things)... system.cpu.dcache.ReadReq_hits::total 881 system.cpu.dcache.WriteReq_hits::total 917 system.cpu.dcache.ReadReq_misses::total 54 system.cpu.dcache.WriteReq_misses:

问题 I need to run a relatively newer version of x86 disk image on gem5. Starting from this guide I used Ubuntu 12.04 disk image with Kernel v3.2.1 as that combination was worked for someone else. After some point, simulator just hangs, please share any ideas about the reason and possible solutions. Thank you! You may find the output on the m5term/telnet below. After that, is the process to prepare the disk image and the kernel for reference. The last part of the terminal of gem5 (m5term/telnet):

问题 I need to run a relatively newer version of x86 disk image on gem5. Starting from this guide I used Ubuntu 12.04 disk image with Kernel v3.2.1 as that combination was worked for someone else. After some point, simulator just hangs, please share any ideas about the reason and possible solutions. Thank you! You may find the output on the m5term/telnet below. After that, is the process to prepare the disk image and the kernel for reference. The last part of the terminal of gem5 (m5term/telnet):

问题 --exec-flags Cache,DRAM show addresses and sizes, but sometimes I just need to see the actual data being sent. I know that this might produce large logs, but that is fine as I'm restricting my area of interest well via --debug-start and -m / --debug-break (used a hack here to just finish the simulation at a tick). https://gem5-users.gem5.narkive.com/VUAhxc7J/how-can-i-trace-data-of-cache mentions using CommMonitor . It is a bit annoying to have to modify the run script, but that's also a

问题 --exec-flags Cache,DRAM show addresses and sizes, but sometimes I just need to see the actual data being sent. I know that this might produce large logs, but that is fine as I'm restricting my area of interest well via --debug-start and -m / --debug-break (used a hack here to just finish the simulation at a tick). https://gem5-users.gem5.narkive.com/VUAhxc7J/how-can-i-trace-data-of-cache mentions using CommMonitor . It is a bit annoying to have to modify the run script, but that's also a

问题 So, I was seeing how some simulations in gem5 are implemented, more specifically, I was having a look at PIMSim (https://github.com/vineodd/PIMSim). I saw they had implemented some pseudo-instructions for the x86 architecture. I have seen these pseudo-instructions are only used in full system mode. For that they have modified the following files: include/gem5/m5ops.h util/m5/m5op_x86.S src/arch/x86/isa/decoder/two_byte_opcodes.isa src/sim/pseudo_inst.hh(cc) I have understood what changes are