A couple of questions about [base + index*scale + disp]

问题

The general form for memory addressing in Intel and AT&T Syntax is the following:

[base + index*scale + disp]
disp(base, index, scale)

My questions are the following:

• Can base and index be any register?
• What values can scale take, is it 1, 2, 4 and 8 (with 1 being the default)?
• Are index and disp interchangeable (with the only difference being that index is a register while disp is an immediate value)?

回答1:

This is described in Intel's manual:

3.7.5 Specifying an Offset
The offset part of a memory address can be specified directly as a static value (called a displacement) or through an address computation made up of one or more of the following components:

• Displacement — An 8-, 16-, or 32-bit value.
• Base — The value in a general-purpose register.
• Index — The value in a general-purpose register. [can't be ESP/RSP]
• Scale factor — A value of 2, 4, or 8 that is multiplied by the index value.

The offset which results from adding these components is called an effective address.

The scale-factor is encoded as a 2-bit shift count (0,1,2,3), for scale factors of 1, 2, 4, or 8. And yes, *1 (shift count = 0) is the default if you write (%edi, %edx); that's equivalent to (%edi, %edx, 1)

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A 16-bit displacement is only encodeable in a 16-bit addressing mode, which uses a different format that can't include a scale factor, and has a very limited selection of which registers can be a base or index. So a mode like 1234(%edx) would have to sign-extend the 1234 to a 32-bit disp32 in the machine code.

Byte offsets from -128 .. +127 can use a short-form 8-bit encoding. Your assembler will take care of this for you, using the shortest valid encoding for the displacement.

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All of this is identical in 64-bit mode for 64-bit addressing modes.

来源：https://stackoverflow.com/questions/27936196/a-couple-of-questions-about-base-indexscale-disp