How many Flip Flops will this code produce?

问题

so I have an exam coming up and I am solving tutes. One of the questions is very basic but I don't think I have the exact logic down for it. It simply gives me a small bit of the code and asks how many Flip Flops will this produce. Could you help me understand how I can find this out? Thanks!

Architecture rtl of ex is
    signal a,b,q, int: bit_vector(3 downto 0);
begin
    process(clk)
    begin
        If  clk = '1' and clk'event then 
            int <= int +1;     
            q <=int;
            a <= b xor q;
        end if;
    end process; 
    b <= int
end;

回答1:

OK, here's the correct - but snarky - answer, with the caveat that it is almost certainly not what the question calls for.

Given the above Architecture declaration, it is clear that there are no assignments to anything other than internal signals. We are not shown the Entity declaration, but from the Architecture we can assume at least an Input port named clk. There may or may not be outputs; we cannot tell, however they are irrelevant as there are no assignments to them.

Therefore the above architecture cannot affect any outputs, so it will be entirely trimmed during the Logic Minimisation phase of synthesis, and generate no Flipflops whatsoever.

来源：https://stackoverflow.com/questions/28408861/how-many-flip-flops-will-this-code-produce