vhdl

问题 VHDL is the worst designed language with the worst syntax that I have ever encountered. Why does this with-select-when code give me an error?: library ieee; use ieee.std_logic_1164.all; entity mux48 is port( mux48dv0:in std_logic_vector(7 downto 0); mux48dv1:in std_logic_vector(7 downto 0); mux48dv2:in std_logic_vector(7 downto 0); mux48dv3:in std_logic_vector(7 downto 0); mux48sv:in std_logic_vector(3 downto 0); mux48ov:out std_logic_vector(7 downto 0) ); end mux48; architectre mux48_df of

问题 Is it possible to use VHDL-2008 hierarchical references / external names to reference Verilog nets? Questa Sim (10.6c) stops the simulation with this error message: vsim-8509: The object class "SIGNAL" of "dut_i.my_net" is different from the class "net" of the denoted object. Here's the VHDL code that fails: alias my_alias is << signal dut_i.my_net : std_logic >>; 回答1: According to the Questa User Manual: Questa SIM supports the IEEE 1076-2008 standard “external name” syntax that allows you

问题 I have a fundamental question on VHDL. Consider the following process: process(Clk) begin if(rising_edge(Clk)) then a <= data_in; b <= a; c <= b; data_out <= c; end if; end process; The above process acts as a delay register, where data_in is output to data_out after 4 clock cycles. From my understanding this happens because signals are assigned parallelly. But then why does the statements inside a process called sequential? For example: process(Clk) begin if(rising_edge(Clk)) then a <= b or

问题 I'm trying to learn VHDL using Peter Ashenden's book 'The Designer's Guide to VHDL', but can't seem to shake the feeling that I have missed a fundamental item related to sensitivity lists. for example a question is "Write a model that represents a simple ALU with integer inputs and output, and a function select input of type bit. if the function select is '0', the ALU output should be the sum of the inputs otherwise the output should be the difference of the inputs." My solution to this is

问题 I have a directory and file structure like this: vunit_multi/ alfa/ run.py ... bravo/ run.py ... The VUnit run.py can run separately. Is there any nice way to combine these multiple separate VUnit runs into a single run with a combined status report? 回答1: Let's say your alfa and bravo run scripts looks something like this from os.path import join, dirname from vunit import VUnit prj = VUnit.from_argv() root = dirname(__file__) lib = prj.add_library("alfa_lib") lib.add_source_files(join(root,

问题 I have a directory and file structure like this: vunit_multi/ alfa/ run.py ... bravo/ run.py ... The VUnit run.py can run separately. Is there any nice way to combine these multiple separate VUnit runs into a single run with a combined status report? 回答1: Let's say your alfa and bravo run scripts looks something like this from os.path import join, dirname from vunit import VUnit prj = VUnit.from_argv() root = dirname(__file__) lib = prj.add_library("alfa_lib") lib.add_source_files(join(root,

问题 I have a directory and file structure like this: vunit_multi/ alfa/ run.py ... bravo/ run.py ... The VUnit run.py can run separately. Is there any nice way to combine these multiple separate VUnit runs into a single run with a combined status report? 回答1: Let's say your alfa and bravo run scripts looks something like this from os.path import join, dirname from vunit import VUnit prj = VUnit.from_argv() root = dirname(__file__) lib = prj.add_library("alfa_lib") lib.add_source_files(join(root,

问题 I have a directory and file structure like this: vunit_multi/ alfa/ run.py ... bravo/ run.py ... The VUnit run.py can run separately. Is there any nice way to combine these multiple separate VUnit runs into a single run with a combined status report? 回答1: Let's say your alfa and bravo run scripts looks something like this from os.path import join, dirname from vunit import VUnit prj = VUnit.from_argv() root = dirname(__file__) lib = prj.add_library("alfa_lib") lib.add_source_files(join(root,

问题 I am just learning vhdl, and am trying to use a 3-input nand gate. The code I have is: G => (A nand B nand C) after 3 ns; but this does not compile. 回答1: I'm not an expert on VHDL but I think you have a couple of mistakes there - it should probably be: G <= not (A and B and C) after 3 ns; i.e. the assignment is in the wrong direction and I'm not sure that nand commutes in the way that you need it to for 3 inputs, hence the use of and for the inputs and then not to invert the output. 回答2: Oh I

问题 I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(my_line, 16); writeline(output, my_line); wait; end process; end behav; which outputs: 16 But how to output instead either: 10 0x10 回答1: Assuming an integer i , and VHDL-2008, you could use: write(output, integer'image(i) & LF); -- Plain integer value write(output, "0x" & to_hstring(to_signed(i, 32)) & LF);