问题
I've used simple makefiles for years, but only recently been assigned the task of learning the ins and outs of a large, complicated set of Autotools-generated makefiles which is used for a code base my employer has bought. In these, I'm running into variable declarations like the following:
QOBJECT_MOCSRCS = $(QOBJECT_HEADER:%.h=.gen/moc_%.cpp) \
$(QOBJECT_SRCS:%.cpp=.gen/moc_%.cpp)
QOBJECT_DEPS = $(QOBJECT_MOCSRCS:%.cpp=.deps/%.Po)
My best guess from context is that these set up lists of names of files to be provided by the build process, eg., QOBJECT_MOCSRCS should end up as a list of (a) .h files, (b) .cpp files, based on the % stem names of a set of intermediate .cpp files which will be generated during the build, in a temporary directory ./gen. This is used to store the moc_%.cpp files which are output as a result of a build of Qt files with Qt's moc tool...what is driving me crazy, is that I have been unable to find anything in any make documentation I've got (mostly the GNU make manual) that tells me what this style of declaration is called, so I can track it down and get a grip on the syntax. The contents of the $() look sort of like rules, and the nearest equivalents in the GNU make manual seem to be rules specifying target-specific variable values, but I have no idea whether this is anywhere near a correct reading. Can anyone point me to an appropriate reference for study?
回答1:
This feature is called substitution references, http://www.gnu.org/software/make/manual/html_node/Substitution-Refs.html#Substitution-Refs
来源：https://stackoverflow.com/questions/16469717/what-kind-of-makefile-variable-assignment-is-this