16-bit bitwise and in VHDL?

问题

If I needed to perform a bitwise AND operation of two 16bit inputs and obtain a 16bit output in VHDL, would I be able to just AND the two inputs and store the result as the output vector? Or would I need to loop through each bit of the inputs, AND them, then store the result in the output vector? Would this work similarly for operations like or and xor?

回答1:

The "and" operator is overloaded in the std_logic_1164 package for std_logic, std_ulogic, std_logic_vector, and std_ulogic_vector (the types typically used). It is also defined for bit and bit_vector (as well as signed and unsigned).

So it is as straightforward as just applying the "and"operator. For example:

architecture rtl of test is
  signal a : std_logic_vector(15 downto 0);
  signal b : std_logic_vector(15 downto 0);
  signal y : std_logic_vector(15 downto 0);
begin
  y <= a and b; -- Or 'y <= a xor b;' or 'y <= a or b;', etc
end architecture rtl;

回答2:

You can just use and.

library IEEE;
use IEEE.std_logic_1164.all;

entity and_gate is
port(
  a: in std_logic_vector(15 downto 0);
  b: in std_logic_vector(15 downto 0);
  q: out std_logic_vector(15 downto 0));
end and_gate;

architecture rtl of and_gate is
begin
  q <= a and b;
end rtl;

http://www.edaplayground.com/x/Xuw

来源：https://stackoverflow.com/questions/35949206/16-bit-bitwise-and-in-vhdl