问题
It seems like there is quite some debate about how to code finite state machines (FSMs) in VHDL. People talk about 1-process, 2-process, or 3-process FSMs as if everyone knew exactly what it means and what each process does. However, I've been unable to find a precise definition, and the examples that exist seem to be contradictory.
This is an objective question: What is the difference in terms of code for each FSM style (1-process, 2-process, 3-process)? I understand that there is a component of personal preference, but certainly it is possible to answer the question objectively and list the advantages of each approach.
Thanks,
回答1:
I try to answer also if it's hard because every person code how he likes and in function of the condition where the hardware has to work (frequency, external paths, ...).
In a state machine you have some elements:
- the inputs
- the outputs
- the current state
- the next state
Next state depends from current state and inputs. To don't have combinatory loops, you need to sample the next state on the event of a clock signal so that it becomes the current state. So, you need a VHDL process to create the flip-flop for the state. In this process you can put all logic that you need to calculate the next state. If your outputs depends only from state you don't need others process.
I don't like to put in the same process combinatory logic when the logic is not very easy (I like so, but it's not mandatory!) so, normally I split the FSM in two process: a first very easy process that sample the next state to have the current one, and one combinatory process where I calculate all outputs and the next state as function of inputs and current state.
In same cases, the outputs need to be sampled: for example, when for problem of frequency, you need to separate the internal paths from external ones, or when the outputs have a big load. In this case, you can add all necessary flip-flops in the first process where you sample the next state or create one or more dedicated process.
But you can have also many variants as number of process: I worked in a code, where every signal is calculated in a dedicated process so the resulting state machine had 20 / 30 process.
来源：https://stackoverflow.com/questions/26618736/what-does-1-2-or-3-process-mean-for-an-fsm-in-vhdl