verilog

问题 Referring to my earlier question here, I've been utilizing tri-states to work with a common bus. I still appear to have some implementation issues. The tri-states use this type of code: assign io [width-1:0] = (re)?rd_out [width-1:0]:{width{1'bz}}; Synthesis and translation goes well. No warnings or errors I wasn't expecting (I was expecting some since this is only a trial run and most of the components don't do anything and will hence be left unconnected). But when I actually try to

问题 I am pretty new to Verilog, but would like to understand it properly. Currently I am making TxRx on FPGA. I noticed that my code is consuming huge amount of logic, although it should not be like that. So I did not wrote my code properly. I know where is mistake, obviously my for loop is making parallelization of expressions (especially because this for loop is nested into another for loop). What would be right way to write code to avoid this. The code is working but it is not efficient. Feel

问题 my code for the design block and the testbench compiles, however when i simulate i'm not getting the correct output. Can anyone tell me where i'm going wrong in my code? Here is the code for testbench: module testbench; reg [511:0]FROM_LS; reg CLK; reg [63:0]TO_IF_ID; initial begin CLK= 0; TO_IF_ID[63:0]=63'b0; FROM_LS[511:480]= 32'b00011_00000_00100_01100_11100_10111_01; FROM_LS[479:448]=32'b00_11000_00100_01111_11111_00011_10000; end always begin #10 CLK= ~ CLK; //FROM_LS[511:448]= ~ FROM

问题 I'm quite a novice to Verilog, but I have an array of 16-elements (each element is 16-bits long) and I wish to find the minimum entry the array, return the minimum, and re-arrange all the entries in the array that come after the minimum so that the array is one contiguous block of entries. I know I have to use a comparator, but I really have no idea where to start with regards to comparing a large group of numbers and determining the minimum. EDIT: What I'm actually making is a priority queue

问题 I'm working on a VGA school-project that I'll synthesize on a FPGA. I'm working with Xilinx and using Verilog as a HDL. The project says that I have to generate a fixed number of particles, display them on screen and, by using the keyboard, I'll have to control the environment for these particles (like the wind, gravity etc.). I can generate one particle with a size of 1 pixel (size is not important) by using: wire p1 =(posx>=part1x[13:4] && posx<=(part1x[13:4]+1) && posy>=part1y[12:4] &&

问题 I know that if I am outputting a binary file in verilog, then I can use the following verilog IO standard function: $fwrite(fd,"%u",32'hABCDE124); But the above command writes 4-byte data into the file. What if the binary data that I want to write is only one-byte, two-bytes or three-bytes? How can I do this? For example, I know the following won't do what I want: $fwrite(fd,"%u",8'h24); $fwrite(fd,"%u",16'hE124); $fwrite(fd,"%u",24'hCDE124); Is there any way that I can write a non 4-byte

问题 I'm trying to create a modules that simulates 4-bit multiplier without using multiplication (*) , need just to use Half and Full adders , so I succeeded to program the solution from some instance , this is the code : module HA(sout,cout,a,b); output sout,cout; input a,b; assign sout = a^b; assign cout = (a&b); endmodule module FA(sout,cout,a,b,cin); output sout,cout; input a,b,cin; assign sout =(a^b^cin); assign cout = ((a&b)|(a&cin)|(b&cin)); endmodule module multiply4bits(product,inp1,inp2

问题 Here I have multiple drivers for 1-bit port x . I want to resolve it by using wand net type. When I check out the schematics, only the least significant bit of input port is connected to port x , while remaining bits as unread. I want all bits of a to be used and assign to x port using AND gate to resolve multiple drivers. module test(input [3:0]a, output [1:0]b); wire [3:0] d [1:0]; wand temp; assign temp=a; inst inst_name (.x(temp),.y(d[1][3]),.z(b[1:0])); assign d[1] = {4'd15}; assign d[0]

问题 I am having trouble understanding why my code have a latch logic [1:0] lru_list [0:3]; always_comb begin if(reset) begin lru_list[0] = 0; lru_list[1] = 0; lru_list[2] = 0; lru_list[3] = 0; end else begin case({access, update, access_index_i < 4}) 3'b101: begin lru_list[0] = lru_list[0] + 1; lru_list[1] = lru_list[1] + 1; lru_list[2] = lru_list[2] + 1; lru_list[3] = lru_list[3] + 1; lru_list[access_index_i] = 0; end 3'b011: begin lru_list[0] = lru_list[0]; lru_list[1] = lru_list[1]; lru_list[2

问题 i am trying out this pretty neat tool called Yosys to synthesize my Verilog designs. i want to export out the FSM in my Verilog design using the Yosys command fsm_export but it does not generate anything. I wonder how is this command supposed to be called? the series of commands i called were: read_verilog qwerty.v ; fsm_export if the generation is successful and i have the FSM in KISS2 format, anyone knows what (open source) tools are there to allow me to visualize the FSM? thanks a bunch!