verilog

问题 I initialize a register reg[1:0] yreg; and manipulate it a bit, i.e., value from prev. iteration of program is shifted to 1 spot when I add in the new value in the 0 spot yreg = SIGNAL; //here SIGNAL is an input to the program And then I want to access the values at the 0 and 1 spots in the register later for a calculation. How can I do this? My initial reaction was yreg[0] and yreg[1] (I normally program in python =) but this is producing an error (line 35 is the line of code that has yreg[0

问题 When I execute the following code I get the then following error, but to my understanding input ports can be of net type, then why does this error occur? module a(inout<or input> i); wand i; endmodule Assertion failed: (0), function draw_net_input_x, file draw_net_input.c, line 727. sh: line 1: 25015 Done /opt/local/lib/ivl/ivlpp -L -F"/tmp/ivrlg2190eb213" -f"/tmp/ivrlg190eb213" -p"/tmp/ivrli190eb213" 25016 Abort trap: 6 | /opt/local/lib/ivl/ivl -C"/tmp/ivrlh190eb213" -C"/opt/local/lib/ivl

问题 In the following code: First, I am loading ROM with data and weight at given address. In the same clock I am doing multiplication of data and weight. Finally, I am extending the number of bits from 16-bit to 23-bit. The code compiles without errors but has warnings. I am unable to solve these warnings. module main_module(extended_out,mux_out,data,weight,clk,en,addr); input clk,en; input [2:0] addr; output [7:0] data,weight; output [15:0] mux_out; output [22:0] extended_out; ram_input a1 (clk,

问题 The Verilog Golden Reference Guide on page 12 warns against unsynthesisable always blocks, and gives templates to be followed to reduce the chances of inadvertently creating unsynthesisable always blocks. However, the guide does not explain why, and in which situations, an always block is not synthesisable. What are the most common reasons for an always block to not be synthesisable? 回答1: Basically every always block is describing a group of flip-flop, a group of latch, or a block of

问题 I get the following error when compiling RISCV VERILOG HDL on Xilinx ISE: It says "Unsupported System Function Call" in the following code at line 296 in module vscale_pipeline 295: ifndef SYNTHESIS 296: PC_WB <= $random; 回答1: Some synthesis tools define the SYNTHESIS macro so that it is easier to skip non-synthesizable code in synthesis using `ifdef SYNTHESIS ... `endif blocks, as is done in this code. Xilinx XST does not define this macro by default, so you have to configure XST manually to

问题 I'm trying to implement a simple verilog code as below: module test1( input ACLK, input RST, output test_output1, output test_output2 ); //wire ACLK; //wire RST; reg test_output1; reg test_output2; assign test_output1 = ACLK; always @(posedge ACLK or negedge RST) begin if(!RST) begin //test_output1 <=0; test_output2 <=0; end else begin //test_output1 <=0; test_output2 <=1; end end endmodule I get the following error message when I try to synthesize it in Xilinx ISE: ==========================

问题 I am having trouble with combination assignment. I do not understand why I cannot use a always combination structure the set my output variables. When I use assign, I do not get the assignment error. I thought assign and always@(*) both means blocking (combinational assignment) module control_unit(input wire [31:0] instruction ,output wire RegDst ,output wire ALUSrc ,output wire RegWrite ,output wire MemRead ,output wire MemWrite ,output wire MemToReg ,output wire Branch ); wire [5:0] opcode;

问题 I used the following code to instantiate 2-D memory in a verilog reg [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF}; reg [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF}; This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done Can anyone elaborate to me as in how that is possible? 回答1: For Altera devices: https://www.altera.com/support/support-resources/design-examples/design-software

问题 I was wondering that in LEX, if i want to parse some code until a special symbol. For example: $display("Hello World"); Here, I want to get $display("Hello World") but except ; . I've already tried this: \$"display".*[^;] , it didn't seem to work. Any help will be appreciated. Thanks. 回答1: . matches any character, and the Kleene star * will match many of whatever precedes it. In this case, you're matching display followed by a list of any other character. That'll happen to include the bit you

问题 I met a problem when trying to write this assertion. I tried to assert the scenario that signal B must be true at least 1 occurrence after signal A is true. The assertion I wrote is below: example : assert property( @(posedge clk) disable iff(reset) A |-> ##[0:$] B[->1]) else `uvm_error(....) The problem is, if during the simulation signal B is never be true after A is true, the uvm_error is not executed. I expected it to be executed, and the simulation reports the message: example: started