Why should an HDL simulation (from source code) have access to the simulator's API?
问题 This is a question inspired by this question and answer pair: call questa sim commands from SystemVerilog test bench The questions asks how Verilog code could control the executing simulator (QuestaSim). I saw similar questions and approaches for VHDL, too. So my question is: Why should a simulation (slave) have power of its simulator (master)? What are typical use cases? Further reading: call questa sim commands from SystemVerilog test bench VerTcl - A Tcl interpreter implemented in VHDL 回答1