VHDL - converting from level sampling to edge triggered - an intuitive explanation?
问题 I have the following code (a primitive "RS-232 signalling" transmitter)... LIBRARY ieee; USE ieee.std_logic_1164.all; entity SerialTX is port( baud_clk : in std_logic; data : in std_logic_vector(7 downto 0); send : in std_logic; serial_out : out std_logic := '0'; busy : out std_logic := '0' ); end entity; ---------------------------------------- architecture behavioural of SerialTX is constant IDLE_BITS : std_logic_vector(10 downto 0) := "00000000001"; signal shifter : std_logic_vector(10