persistent-memory

问题 When using persistent memory like Intel optane DCPMM, is it possible to see partial result after reboot if system crash(power outage) in execution of movnt instruction? For: 4 or 8 byte movnti which x86 guarantees atomic for other purposes? 16-byte SSE movntdq / movntps which aren't guaranteed atomic but which in practice probably are on CPUs supporting persistent memory. 32-byte AVX vmovntdq / vmovntps 64-byte AVX512 vmovntdq / vmovntps full-line stores bonus question: MOVDIR64B which has

问题 When using persistent memory like Intel optane DCPMM, is it possible to see partial result after reboot if system crash(power outage) in execution of movnt instruction? For: 4 or 8 byte movnti which x86 guarantees atomic for other purposes? 16-byte SSE movntdq / movntps which aren't guaranteed atomic but which in practice probably are on CPUs supporting persistent memory. 32-byte AVX vmovntdq / vmovntps 64-byte AVX512 vmovntdq / vmovntps full-line stores bonus question: MOVDIR64B which has

问题 Commonly, cacheline is 64B but atomicity of non-volatile memory is 8B. For example: x[1]=100; x[2]=100; clflush(x); x is cacheline aligned, and is initially set to 0 . System crashs in clflush(); Is it possible x[1]=0 , x[2]=100 after reboot？ 回答1: Under the following assumptions: I assume that the code you've shown represents a sequence of x86 assembly instructions rather than actual C code that is yet to be compiled. I also assume that the code is being executed on a Cascade Lake processor

问题 Closed. This question does not meet Stack Overflow guidelines. It is not currently accepting answers. Want to improve this question? Update the question so it's on-topic for Stack Overflow. Closed 12 days ago . Improve this question I'm a little confused about Intel Optane DC. I want that my Optane DC will be able to perform as DRAM and storage both. On the one hand, I understood that only "Intel Optane DC Persistent Memory DIMM" is able to perform as DRAM.That it because he has 2 modes

问题 I want to read and write to a persistant memory(for testing now ddr is connected) in my PCIe device (FPGA) on an Intel Linux system. The memory is exposed in a particular bar (say bar 2). How to access this persistant memory. I looked into examples in PMDK library, but I couldn't find any. When I looked into libpmem library I did find mapping api pmem_map_file() but there is no provision to select the bars. Is it possible to use mmap() call? Currently I am using as shown below to access my

问题 I am trying to use some of the uncore hardware counters, such as: skx_unc_imc0-5::UNC_M_WPQ_INSERTS . It's supposed to count the number of allocations into the Write Pending Queue. The machine has 2 Intel Xeon Gold 5218 CPUs with cascade lake architecture, with 2 memory controllers per CPU. linux version is 5.4.0-3-amd64. I have the following simple loop and I am reading this counter for it. Array elements are 64 byte in size, equal to cache line. for(int i=0; i < 1000000; i++){ array[i]

问题 I am trying to find configuration or memory access pattern for Intel's clwb instruction that would not invalidate cache line. I am testing on Intel Xeon Gold 5218 processor with NVDIMMs. Linux version is 5.4.0-3-amd64. I tried using Device−DAX mode and directly mapping this char device to the address space. I also tried adding this non-volatile memory as a new NUMA node and using numactl --membind command to bind memory to it. In both cases when I use clwb to cached address, it is evicted. I