makefile

问题 How can I execute a shell script before building my targets in a Makefile, and see the output as it runs? I have a script called prepare.sh that generates a bunch of .pyx files. The .pyx files are the starting point of my build process involving make. It goes from .pyx -> .c -> .o -> .so I don't like having to run prepare.sh separately prior to make. I'd like make to run it for me. I got it to work but I don't see the output of the command. I'd like to see it. This is what I have now: PATH :=

问题 This is how my directory looks like: /project makefile /ceda_lib makefile files.... /general makefile files.... /CLI makefile files.... /objects files.o Makefile(main): 1 #start other makefiles 2 3 4 o= ./objects 5 DEPS= Affine.hpp CEDA.hpp generalParameters.hpp generalFunctions.hpp 6 OBJ= $o/main.o $o/Affine.o $o/generalFunctions.o 7 CC=g++ 8 CFLAGS= -Wall -g -I. 9 export CC 10 export CFLAGS 11 export DEPS 12 13 all: 14 ▸---+$(MAKE) -C general 15 ▸---+$(MAKE) -C ceda_lib 16 ▸---+$(MAKE) -C

问题 This is how my directory looks like: /project makefile /ceda_lib makefile files.... /general makefile files.... /CLI makefile files.... /objects files.o Makefile(main): 1 #start other makefiles 2 3 4 o= ./objects 5 DEPS= Affine.hpp CEDA.hpp generalParameters.hpp generalFunctions.hpp 6 OBJ= $o/main.o $o/Affine.o $o/generalFunctions.o 7 CC=g++ 8 CFLAGS= -Wall -g -I. 9 export CC 10 export CFLAGS 11 export DEPS 12 13 all: 14 ▸---+$(MAKE) -C general 15 ▸---+$(MAKE) -C ceda_lib 16 ▸---+$(MAKE) -C

问题 What's the difference on Windows with cmake and eclipse and MingW if I choose "Eclipse MingW Makefile" or "Eclipse Unix Makefile"? With the MingW one I always get an error with "sh.exe" (that vanishes if I re-hit "Configure"), with the Unix one I always have to specifiy windres manually because cmake can't find it. Does this make any difference for Eclipse or something else? Both generated Makefiles work with Eclipse and MingW and compile my project. What Makefile should I choose? And why?

问题 Utility: NMake Platform : Windows 7 I have the following Makefile FILE = $(shell) *.c FILE += $(shell) *.cpp exec: @echo $(FILE) This works perfectly fine with make. This throws up the following error with nmake makefile(2) : fatal error U1036: syntax error : too many names to left of '=' Stop. What could be the reason? Without the line FILE += $(shell) *.cpp nmake works perfectly fine. 回答1: The += syntax is a GNU Make extension that was pioneered in Sun's make in the late 80s. It is not part

问题 I have a header file myheader.h and a static library libmylib.a file in directory1. In directory2, I'm writing a program which uses them. Suppose I have main.c in directory2 which uses myheader.h and libmylib.a. How do I create a Makefile to compile and link them? Right now, in my main.c, I have added #include "../directory1/myheader.h" Here's my Makefile at the moment: CC = gcc INCLUDES = -I CFLAGS = -g -Wall $(INCLUDES) main: main.o ../directory1/libmylib.a $(CC) main.o ../directory1

问题 I see the error when I try to build Android Open Project Source . ninja: no work to do. [1/1] out/soong/.bootstrap/bin/soong_build out/soong/build.ninja FAILED: out/soong/build.ninja out/soong/.bootstrap/bin/soong_build -t -l out/.module_paths/Android.bp.list -b out/soong -n out -d out/soong/build.ninja.d -o out/soong/build.ninja Android.bp internal error: Could not find a supported mac sdk: ["10.10" "10.11" "10.12" "10.13"] ninja: build stopped: subcommand failed. 20:17:47 soong bootstrap

问题 I am not sure whether I have described the question properly, but currently I am solving this problem in the following way QUOTEDSTR := "hello world" NORMALSTR := $(shell echo $(QUOTEDSTR)) Is there a more built-in way that 'make' can do this without calling shell? Thanks 回答1: Another option: NORMALSTR := $(patsubst "%",%,$(QUOTEDSTR)) Beta's answer will remove every quote in the string. The above solution will ONLY remove quotes that appear at the beginning and end. For example: QUOTEDSTR :=

问题 I am writing a Makefile, which will list all headers included by a.cpp, b.cpp and c.h files. However, I got the error of unexpected EOF. Similar questions are always caused by the line terminator, like they used CRLF instead of LF for an EOL. However, my Text editor was set to using LF and I recheck this by delete all EOL and re-added. Unfortunately, the error still remains. Here are the codes: #!/bin/bash list-header: for file in a.cpp b.cpp b.h do echo "$file includes headers: " grep -E '^

问题 I have a GNU Makefile (version 3.81) that looks like the following: .PHONY: SPOneDot SPOneDot: ifndef X X=0.05 $$(info X undefined, changed to $X) endif ifndef Y Y=0.05 $$(info Y undefined, changed to $Y) endif python ./Submit3DSP.py -f OneDot.qdt -x $(X) -y $(Y) I execute with the following command line: make X=0.1 Y=0.1 SPOneDot but I get the following result: ifndef X make: ifndef: Command not found make: *** [SPOneDot] Error 127 I've looked in the makefile documentation and seen others