machine-instruction

Why can assembly instructions contain multiplications in the “lea” instruction?

让人想犯罪 __ 提交于 2019-12-03 06:58:01
I am working on a very low level part of the application in which performance is critical. While investigating the generated assembly, I noticed the following instruction: lea eax,[edx*8+8] I am used to seeing additions when using memory references (e.g. [edx+4]), but this is the first time I see a multiplication. Does this mean that the x86 processor can perform simple multiplications in the lea instruction? Does this multiplication have an impact on the number of cycles needed to execute the instruction? Is the multiplication limited to powers of 2 (I would assume this is the case)? Thanks

what does machine value type “other” mean in llvm SDnodes

£可爱£侵袭症+ 提交于 2019-12-02 07:13:37
问题 I am trying to understand more deeply the instruction selection process in llvm and for that I am debuging step-by-step the CodeGenAndEmitDAG function. I have printed a small function (see below) just before the combine step - the first step in the above function. In the graph I see blue lines and it seems that they are always pointing at "ch" , which I think means "other" machine value type. What I don't understand is the meaning of the blue lines... what is this dependency ? And, am I right

what does machine value type “other” mean in llvm SDnodes

喜夏-厌秋 提交于 2019-12-02 00:26:20
I am trying to understand more deeply the instruction selection process in llvm and for that I am debuging step-by-step the CodeGenAndEmitDAG function. I have printed a small function (see below) just before the combine step - the first step in the above function. In the graph I see blue lines and it seems that they are always pointing at "ch" , which I think means "other" machine value type. What I don't understand is the meaning of the blue lines... what is this dependency ? And, am I right about the meaning of "ch" ? is it "other" ? Dashed blue arrows represent non-dataflow dependencies

Is there any performance difference between greater than and greater than or equal?

微笑、不失礼 提交于 2019-12-01 16:37:34
On today's modern processors, is there any performance difference between greater than and greater than or equal comparison for a branch condition? If I have a condition that could just as easily be either, is there any slight advantage to choosing > over >= or vice-versa? (This would be for a compiled language on Intel or AMD hardware) There shouldn't be any noticeable difference between comparing different predicates, because of the way they're computed (beware I haven't read the x86 manuals in detail so it may work different): Most instructions produce several flags as a byproduct, usually

Is there any performance difference between greater than and greater than or equal?

不打扰是莪最后的温柔 提交于 2019-12-01 14:38:50
问题 On today's modern processors, is there any performance difference between greater than and greater than or equal comparison for a branch condition? If I have a condition that could just as easily be either, is there any slight advantage to choosing > over >= or vice-versa? (This would be for a compiled language on Intel or AMD hardware) 回答1: There shouldn't be any noticeable difference between comparing different predicates, because of the way they're computed (beware I haven't read the x86

How is data, address and Instruction differentiated in Processor/Register/memory?

折月煮酒 提交于 2019-12-01 01:33:19
In Processor, how are Data, Address and instructions are differentiated? When a program is executed, how is processor differentiate instructions when everything is in 0 s and 1 s and register`s load both data, addresses? The processor only does what you tell it to do. As you noted, the processor can't tell the difference between "data" and "code" in memory: it's all just a sequence of bytes. It's what you tell it to do with those bytes that defines how it's treated. When a program is compiled, the generated executable file has information in it that says which parts are code and which parts

What's the purpose of the rotate instructions (ROL, RCL on x86)?

好久不见. 提交于 2019-11-28 17:14:39
I always wondered what's the purpose of the rotate instructions some CPUs have (ROL, RCL on x86, for example). What kind of software makes use of these instructions? I first thought they may be used for encryption/computing hash codes, but these libraries are written usually in C, which doesn't have operators that map to these instructions. Has anybody found an use for them? Why where they added to the instructions set? Rotates are required for bit shifts across multiple words. When you SHL the lower word, the high-order bit spills out into the carry. To complete the operation, you need to

What x86 instructions take two (or more) memory operands?

不打扰是莪最后的温柔 提交于 2019-11-27 09:35:33
I thought that there was zero. But, I see here, Instructions with two memory operands are extremely rare I can't find anything that explains what instructions, though rare, exist. What are the exceptions? Peter Cordes I can't find anything that explains the rarity. An x86 instruction can have at most one ModR/M + SIB + disp0/8/32. So there are zero instructions with two explicit memory operands. The x86 memory-memory instructions all have at least one implicit memory operand whose location is baked in to the opcode, like push which accesses the stack, or the string instructions movs and cmps .

How was the first compiler written?

旧街凉风 提交于 2019-11-26 13:55:47
I heard about the chicken and the egg and bootstrapping. I have a few questions. What wrote the first compiler that converted something into binary instructions? Is assembly compiled or translated into binary instructions? ...I'd find it hard to believe they wrote a compiler in binary. Assembly instructions are (generally) a direct mapping to opcodes, which are (multi-)byte values of machine code that can be directly interpreted by the processor. It is quite possible to write a program in opcodes directly by looking them up from a table (such as this one for the 6039 microprocessor , for

What x86 instructions take two (or more) memory operands?

天大地大妈咪最大 提交于 2019-11-26 11:38:13
问题 I thought that there was zero. But, I see here, Instructions with two memory operands are extremely rare I can\'t find anything that explains what instructions, though rare, exist. What are the exceptions? 回答1: I can't find anything that explains the rarity. An x86 instruction can have at most one ModR/M + SIB + disp0/8/32. So there are zero instructions with two explicit memory operands. The x86 memory-memory instructions all have at least one implicit memory operand whose location is baked