intel

问题 I have been working on an c/c++ OpenCL solution for the past few weeks now. For my solution, I need to pass a class from my CPU(Host) to GPU(Device). When I try to pass the class as an argument it gives an error "Unknown Type-Identifier Class". My doubt whether OpenCL on Intel Platform does it allow us to pass a class to kernel or any work around is available for it. In CUDA I have seen some examples and it works perfectly fine for the platform. However, with respect to OpenCL I am not able

问题 I am trying to get the code (see far below) working on Ubuntu. The code uses clock_gettime() . I think I have successfully linked to librt.a: **** Build of configuration Debug for project test **** make -k all Building file: ../src/test.cpp Invoking: Intel Intel(R) 64 C++ Compiler icpc -g -I/usr/include/boost -std=c++0x -MMD -MP -MF"src/test.d" -MT"src/test.d" -c -o "src/test.o" "../src/test.cpp" Finished building: ../src/test.cpp Building target: test Invoking: Intel Intel(R) 64 C++ Linker

问题 There isn't a lot of information about the L4 cache, but as far as I know, it was used in the 4th and 5th generation of Intel processors(2013-2014), but it's gone from the current generation. Was the L4 bad, ineffective or something? 回答1: For Haswell and Broadwell, eDRAM L4 cache tags are resident in the on-chip L3 cache. Although this setup simplifies the LLC design and allows earlier tag checking for fetches from the processor, it makes the accessing to eDRAM LLC from other devices (e.g.,

问题 All the Intel CPUs in the last decade (at least) include a set of performance monitors that count a variety of events. Do the latest Intel CPUs, Core i3, i5 and i7 (aka Nehalem) provide a mechanism to count Instructions Per Clock (IPC)? If so, how are they used? If this is possible, I'll probably be writing the code for this in Assembly, but Windows or Linux system calls may also come in useful. 回答1: Yes, the Vtune from Intel (linux and windows) can measure IPC. If you want to measure it by

问题 This question is unlikely to help any future visitors; it is only relevant to a small geographic area, a specific moment in time, or an extraordinarily narrow situation that is not generally applicable to the worldwide audience of the internet. For help making this question more broadly applicable, visit the help center. Closed 6 years ago . I am trying to learn up to date x86 assembly all from old 386 base instructions through all the sse additions up until now. I read some things like SSE5

问题 I have a number of questions about Intel PT (have been trying to decode the manual but is very difficult). My questions are: I am trying to find out if Intel PT can be disabled or reconfigured from within an OS, or, more generally, from within the system it is providing a trace of. Does Intel PT generate events on writes to specific registers - such as CR3, IDTR, etc Can Intel PT write values back to the system - i.e. can an external debugging machine actively perform writes to register,

问题 According to the Intel 64 and IA-32 Architectures Software Developer's Manual the LOCK Signal Prefix "ensures that the processor has exclusive use of any shared memory while the signal is asserted". That can be a in the form of a bus or cache lock. But - and that's the reason I'm asking this question - it isn't clear to me, if this Prefix also provides any memory-barrier. I'm developing with NASM in a multi-processor environment and need to implement atomic operations with optional acquire

问题 Is there any way of using Android emulator on High Sierra (10.13)? When I run ./HAXM\ installation -u It says: HAXM silent installation only supports macOS from 10.8 to 10.12 ! 回答1: The command line installation doesn't work and gives unsupported mac os version error, while the installation through IntelHAXM_6.2.1.mpkg works but kext is not loaded due to "Approved Kernel Extension Loading" changes, So you will need to allow the extensions from Intel and restart your mac, then launch the

问题 This example comes from 64-IA-32 Architectures Software Developers Manual. And I cannot understand why store of CPU #0 must be visible for other processors? In that concrete example ( when r1 = 1, r2 = 1) I agree that it is obvious that store made by CPU #0 must be retired firstly- I mean the 1 value must be in memory/cache in fact ( not in store buffer). But what about general case? Is it possible the following situation: CPU#0 stored: mov [_x], 1 but it was stored in CPU#0's store buffer ,

问题 When I query some OpenGL info then I get the following statements: Vendor: Intel Open Source Technology Center WindowManager: Mesa DRI Intel(R) HD Graphics 520 (Skylake GT2) OpenGL version: 4.5 (Core Profile) Mesa 17.0.1 GLSL version: 4.50 But my laptop CPU/GPU Intel 6200U with Intel HD 520 (Ubuntu 17.04) supports according to Intel Product Specification only OpenGL 4.4 . Can anybody say something about this? Is the OpenGL query wrong? Thanks 回答1: If you are using the open source driver on