hdl

问题 I have tried this multiple ways, I am a bit desperate now. I have tried to make this clock in my testbench the problem is in simulation it doesn't work or my simulation seems to freeze. I know it has to be the clock. initial begin forever begin clk = 0; #10 clk = ~clk; end end initial begin reset = 0; #15 L = 0; R = 0; H = 0; #20 L = 0; R = 0; H = 1; #25 L = 0; R = 1; H = 0; #30 L = 0; R = 1; H = 1; #35 L = 1; R = 0; H = 0; #45 L = 1; R = 0; H = 1; #50 L = 1; R = 1; H = 0; #55 L = 1; R = 1; H

问题 I am working on a project which requires data to be sent FROM PC TO FPGA,which processes the data and sends it BACK TO PC. The board I am using is Atlys™ Spartan-6 FPGA Development Board. The data is to be sent as 1 byte , because 1 byte is processed at each rising edge of the clock. Could you please suggest me ways of sending data to FPGA ? Thanks 回答1: Pick some method of communication that you have access to IP (intellectual property) cores for. For example, if you can readily access a UDP

问题 I am working on a project which requires data to be sent FROM PC TO FPGA,which processes the data and sends it BACK TO PC. The board I am using is Atlys™ Spartan-6 FPGA Development Board. The data is to be sent as 1 byte , because 1 byte is processed at each rising edge of the clock. Could you please suggest me ways of sending data to FPGA ? Thanks 回答1: Pick some method of communication that you have access to IP (intellectual property) cores for. For example, if you can readily access a UDP

问题 My code for a reaction tester works perfectly and as it should in simulation. But when I move it to my FPGA device it just stalls as soon as I press the start button and I cannot figure out what goes wrong as it is working perfectly in simulation. The concept is, when reset is pressed display Hi on the screen, when start is pressed, pick a random value from LFSR and count up to max value, thus making it a random delay. When max count for this reg is reached turn on the led, start the timer

问题 i have a module parameter that is an array of a predefined struct. I set the default size of this array as 1 element. The idea is to override it with the appropriate size at the time of instantiation. The way i show below doesn't override the size. It only overides the first value. I can see why it would do this as the size field is not parameterized. Is there a better way than to pass a parameter for the size? Thank you for the help. module reg_slave #(parameter reg_pkg::defval_pair [0:0]

问题 In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog? 回答1: There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource. Also

问题 In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog? 回答1: There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource. Also

问题 In designing a circuit in verilog using top-down method, I can start from the behavior of a circuit followed by defining the details in every module to construct a structural circuit that is synthesizable. But how can I know if my code is synthesizable? Are there any guidelines to follow to support synthesis in verilog? 回答1: There is a 'standard', IEEE 1364.1 but as Martin pointed out each tool supports whatever it wants. I recommend the Xilinx XST User Guide if you need a free resource. Also

问题 Where Can I find algorithm details for holistic word recognition? I need to build a simple OCR system in hardware (FPGAs actually), and the scientific journals seems so abstract? Are there any open source (open core) codes for holistic word recognition? Thanks 回答1: For an algorithm that is quite suitable for FPGA implementation (embarrassingly parallel) you might look at: http://en.wikipedia.org/wiki/Cross-correlation It is fast, and easily implemented. The only thing is: it recognizes a

问题 Where Can I find algorithm details for holistic word recognition? I need to build a simple OCR system in hardware (FPGAs actually), and the scientific journals seems so abstract? Are there any open source (open core) codes for holistic word recognition? Thanks 回答1: For an algorithm that is quite suitable for FPGA implementation (embarrassingly parallel) you might look at: http://en.wikipedia.org/wiki/Cross-correlation It is fast, and easily implemented. The only thing is: it recognizes a