gnu-make

we have some C++ code that we need to create a make file in. Each .h and .C pair create an object and then some objects are linked together to form a executable. Pretty standard stuff. This non-gnu make command just builds all the files into object in a directory %.o:%.C $(CC) $(CPFLAGS) -c $< What this does is for each %.C file (ie every .C file) build a corresponding .o file. Does anybody know how to do this with gmake? Cheers Mark The syntax you've shown is called a pattern rule in GNU make parlance, and it forms the corner stone of your solution. All you need is to add a way to get the

This is slightly different from Can a Makefile execute code ONLY when an error has occurred? . I'd like a rule or special target that is made whenever an error occurs (independent of the given target; without changing the rule for every target as the other answer seems to imply with the || operator). In dmake there is special target .ERROR that is executed whenever an error condition is detected . Is there a similar thing with GNU make? (I'm still using GNU make 3.81, but I didn't find anything in the documentation of the new GNU make 4.0 either) Gnu doesn't support it explicitly, but there's

I'm running the following kind of pipeline: digestA: hugefileB hugefileC cat $^ > $@ rm $^ hugefileB: touch $@ hugefileC: touch $@ The targets hugefileB and hugefileC are very big and take a long time to compute (and need the power of Make). But once digestA has been created, there is no need to keep its dependencies: it deletes those dependencies to free up disk space. Now, if I invoke 'make' again, hugefileB and hugefileC will be rebuilt, whereas digestA is already ok. Is there any way to tell 'make' to avoid to re-comile the dependencies ? NOTE: I don't want to build the two dependencies

I need to take a parameter in my Makefile that consists of a host identifier in the form host[:port] where the colon and port are optional. So all of the following are valid: foo.example.com ssl.example.com:443 localhost:5000 etc. I want to split the string on the optional colon and assign the values to variables, so that HOST contains foo.example.com , ssl.example.com , localhost , etc., and PORT contains 80 (the default port), 443, and 500 respectively. # Retrieves a host part of the given string (without port). # Param: # 1. String to parse in form 'host[:port]'. host = $(firstword $(subst

I have the following piece of makefile: CXXFLAGS = -std=c++0x -Wall SRCS = test1.cpp test2.cpp OBJDIR = object OBJS = $(SRCS:%.cpp=$(OBJDIR)/%.o) all: test1 release: clean test1 test1: $(OBJS) $(CXX) -o $@ $(OBJS) $(OBJDIR)/%.o: %.cpp $(CXX) $(CXXFLAGS) -MD -c -o $@ $< -include $(SRCS:.cpp=.d) clean: rm -rf $(OBJDIR)/* .PHONY: all clean release Now if I try to invoke "make -j4 release" the clean target often gets execute in the middle of building files which causes compilation to fail. My question is how to ensure that the clean target has completed before starting the release build. My

How can I convert a Cygwin style path ( /cygdrive/c/foo/bar ) to Windows style ( C:/foo/bar ) (yes, with / going forward) in a GNU makefile? I have the situation of using Cygwin's make with a GCC that does not understand Cygwin style paths, so paths relative to the makefiles location that are produced by make are not accepted by the compiler. Use the shell function to execute the cygpath utility with the -w flag. Example: BAR := /cygdrive/c/foo/bar WIN_BAR := $(shell cygpath -w ${BAR}) cygpath accepts a lot of additional options. See the man page for details. 来源： https://stackoverflow.com