gnu-make | 易学教程

Convert Cygwin path to Windows path in a makefile

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问题 How can I convert a Cygwin style path ( /cygdrive/c/foo/bar ) to Windows style ( C:/foo/bar ) (yes, with / going forward) in a GNU makefile? I have the situation of using Cygwin's make with a GCC that does not understand Cygwin style paths, so paths relative to the makefiles location that are produced by make are not accepted by the compiler. 回答1: Use the shell function to execute the cygpath utility with the -w flag. Example: BAR := /cygdrive/c/foo/bar WIN_BAR := $(shell cygpath -w ${BAR})

Parallel makefile requires dependency ordering

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问题 I have the following piece of makefile: CXXFLAGS = -std=c++0x -Wall SRCS = test1.cpp test2.cpp OBJDIR = object OBJS = $(SRCS:%.cpp=$(OBJDIR)/%.o) all: test1 release: clean test1 test1: $(OBJS) $(CXX) -o $@ $(OBJS) $(OBJDIR)/%.o: %.cpp $(CXX) $(CXXFLAGS) -MD -c -o $@ $< -include $(SRCS:.cpp=.d) clean: rm -rf $(OBJDIR)/* .PHONY: all clean release Now if I try to invoke "make -j4 release" the clean target often gets execute in the middle of building files which causes compilation to fail. My

Using GNU Make to build both debug and release targets at the same time

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问题 I'm working on a medium sized project which contains several libraries with interdependence's which I've recently converted over to build using a non-recursive makefile. My next goal is to enable building of both debug and release builds out of the same source tree at the same time (make debug;make release). My first step was to make debug and release targets which contained the correct build flags. I did this using target specific variables, like this: CXXFLAGS=-Wall -Wextra -Werror -DLINUX

GNU make: “Nothing to be done for 'target'” vs. “'target' is up to date”

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How does GNU make decide which of the messages to emit? The Makefile I am using causes Nothing to be done for 'target' messages to be emitted when the target is up do date. But I think 'target' is up to date would be more appropriate. The chief difference is in whether gmake has a rule to build the target or not. If there is no rule for the target, but the target exists, then gmake will say, "Nothing to be done", as in, "I don't know how to update this thing, but it already exists, so I guess there's nothing to be done." If there is a rule, but the target is already up-to-date, then gmake will

make deleting dependency files

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I'm not sure if it's gmake or gcc that I don't understand here. I'm using the -MM and -MD options to generate dependency rules for the Unit Testing framework I'm using. Specifically: $(TEST_OBJ_DIR)/%.d: $(TEST_SRC_DIR)/%.cpp @$(CPPC) -MM -MD $< -o $@ @sed -i -e 's|$.*$\.o:|$(OBJ_DIR)/\1.o $(TEST_OBJ_DIR)/\1.d $(TEST_OBJ_DIR)/\1.o:|' $@ -include $(TEST_DEP_FILES) When I run make , after all binaries are linked (properly), I see the following extra (unexplained) line before make exits rm test/obj/dice.d test/obj/regex.o test/obj/inventoryContainer.d test/obj/color-string.d test/obj/dice.o

Makefile pattern rule for no extension?

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问题 I have a bunch of applications that are built with the same type of make rule: apps = foo bar baz all: $(apps) foo: foo.o $(objects) $(link) bar: bar.o $(objects) $(link) baz: baz.o $(objects) $(link) If they had an extension (for example .x ) I could make a pattern rule like: %.x: %.o $(objects) $(link) and I wouldn't have to write out a new rule for each app. But they don't have an extension, and I'm pretty sure that: %: %.o $(objects) $(link) won't work (because it specifies that to build

GNU make: Multiple targets in a single rule [duplicate]

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问题 This question already has answers here : Closed 7 years ago . Possible Duplicate: GNU Makefile rule generating a few targets from a single source file If I have a Makefile rule like this: a b c: echo "Creating a b c" touch a b c output: a b c cat a b c > output and I run make -j9 output make sees the 3 dependencies (a,b,c), looks for how to produce them: (the "a b c" rule above), but what happens next? Should it not realize that the "a b c" rule only needs to be run once to create all 3

GCC build time doesn't benefit much from precompiled headers

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I have a huge project, something about 150 000 LOC of C++ code. Build time is something about 15 minutes. This project consists of many sub-projects of different sizes. I have built separate precompiled headers for each subproject, but when I use them build time stays roughly the same. It seemed that build time is 5-10% percent less, not more. Precompiled headers is definitely used, I use -Winvalid-pch option and I have tried to compile with -H compiler option, my precompiled headers appears in output with 'bang' symbol, that means that compiler is able to use precompiled header. All my

GNU make's -j option

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问题 Ever since I learned about -j I've used -j8 blithely. The other day I was compiling an atlas installation and the make failed. Eventually I tracked it down to things being made out of order - and it worked fine once I went back to singlethreaded make. This makes me nervous. What sort of conditions do I need to watch for when writing my own make files to avoid doing something unexpected with make -j? 回答1: I think make -j will respect the dependencies you specify in your Makefile; i.e. if you

How do I specify in a Makefile.am script that I only want to compile object .o files?

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I have a Makefile.am which will be responsible for building a final application binary: project/src/Makefile.am Also in the src directory is a sub-directory called ctrnn which contains an additional Makefile.am : project/src/ctrnn/Makefile.am Now, ctrnn/Makefile.am should only generate object .o files with the idea being that the top-level Makefile.am should use the object files generated in subdirectory ctrnn to build the binary. This is the ctrnn/Makefile.am : SOURCES = network.cpp\ neuron.cpp AM_CPPFLAGS= @CXXFLAGS@ Based on this Makefile.am file, I want to end up with network.o and neuron