gnu-make

I can't figure out a way to define a generic pattern rule for the following kind of production with make: require xyzzy-en_US.ext2 from xyzzy.ext0 via xyzzy.ext1 . This works: all: xyzzy-en_US.ext2 # to be compiled from xyzzy.ext0 %.ext1 : %.ext0 # produce xyzzy.ext1 %-en_US.ext2 : %.ext1 # produce xyzzy-en_US.ext2 But how to generalize the locale part of the second rule? Or do I need to generate rules for all different locales? Neither of these work: %-??_??.ext2 : %.ext1 # ... %.ext2 : $(@,%-??_??.ext2,%.ext1) # ... There is no good way to do this with Make (regex handling is high on my

I am using GNU Make to build a C/C++ project that many people will use. The makefile attempts to be general because there are many optional files in this project and each user selects those files through a MATLAB interface which are then provided to the makefile via command line arguments (make target OPTS='XYZ' etc...). When I use the makefile it correctly identifies the correct object dependencies, then proceeds to find the source prerequisites for those objects and build them. However, every time it tries to execute an object rule I get an error saying "Abort trap: 6" right after the gcc

I'm working on compiling a library in windows with GCC and Make. When I run make , I get the following error: unrecognized command line option '-mno-cygwin' I saw this post on SO, but it doesn't necessarily seem like the same issue, and I don't understand how to downgrade my system to a version of GCC (or Make) that supports the flag I need to use in order to compile. Could someone please try to point me in the right direction, or if you've run into this problem offer a solution? I'm running Windows 8.1 pro, GCC 5.4.0, make 4.2.1. I can post more info if it is necessary to help me. matzeri The

In Make this flag exists: -l [load], --load-average[=load] Specifies that no new jobs (commands) should be started if there are others jobs running and the load average is at least load (a floating-point number). With no argument, removes a previous load limit. Do you have a good strategy for what value to use for the load limit ? It seems to differ a lot between my machines. Maxim Egorushkin Acceptable load depends on the number of CPU cores. If there is one core, than load average more than 1 is overload. If there are four cores, than load average of more than four is overload. People often

I am trying to write a Makefile with my source and object files separated and I can't seem to figure out the proper way to accomplish this. I have two methods that work but I'm hoping someone can point the "correct" way to do this is. My project is separated into a src and obj folder with the Makefile at the same level as these. The first method uses the wildcard function to find the source files in src then uses text replacement to determine the corresponding object files. SRC = $(wildcard src/*.cpp) OBJ = $(SRC:.cpp=.o) prog: $(OBJ) $(CC) $(CFLAGS) $(LDFLAGS) $(LIBS) -o prog $(patsubst src/

I have a directory images/ that I want to copy to build/images/ from within a Makefile. The directory might contain multiple levels of subdirectories. What would be the most elegant way to do that? I want: avoid a full directory copy on each make run (i.e. no cp -r ) guaranteed consistency (i.e. if a file changed in images/ it should be automatically updated in build/images/ ) avoid to specify a rule for each image and each subdirectory in the Makefile solve the issue within make , so no rsync or cp -u if possible I am using GNU make, so GNU specific stuff is allowed. liori Well, I'd just use

Is it possible to perform a make clean from the parent directory which also recursively cleans all sub-directories without having to include a makefile in each sub-directory? For example, currently in my Makefile, I have something like: SUBDIRS = src, src1 .PHONY: clean subdirs $(SUBDIRS) clean: $(SUBDIRS) rm -rf *.o *~ core .depend .*.cmd *.ko *.mod.c $(SUBDIRS): $(MAKE) -C $(SUBDIRS) clean However, this requires me to have a Makefile in both src and src1. Otherwise, I would get the error No rule to make target clean Since I only want to run the command "rm -rf *.o ~ core .depend . .cmd *.ko