gnu-make

I currently try to write a Makefile that build properly a project which contains a git submodule. This submodule have its own set of makefiles and produce several targets at once, including some libraries. This Makefile should have the following properties. Don't rebuild twice the submodule even with parallel build. Update the submodule targets when the submodule code has changed (maybe because I navigated through the revisions of the main repository). Re-link the main project when the submodule library have changed. Don't copy-paste the Makefiles of the submodule in the top-level project (i.e

I am using CMake 3.8.2, GNU make 4.2.1 and GCC 6.4.0 for my C++14 project and I noticed a strange behavior when building. I am using CMake for an out-of-source build in a sub-folder called "build" where I run cmake .. followed by make . CMake runs fine without any errors and make will build all source files like I expect until it is done compiling and starts linking them. It will then fail with an error [ 83%] ... [100%] Linking CXX executable myproject /usr/bin/ld: some-source-file.cc.o: undefined reference to symbol '_ZNKSt7__cxx1118basic_stringstreamIcSt11char_traitsIcESaIcEE3strEv@@GLIBCXX

For a project of mine I am automatically generating makefiles and including them, like this: all: @echo 'SUCCESS is $(SUCCESS)' clean: rm depend.mk depend.mk: @echo 'Creating $@' @echo 'SUCCESS := 1' > $@ .PHONY: all clean include depend.mk This works, but the include line generates a warning message: $ make Makefile:13: depend.mk: No such file or directory Creating depend.mk SUCCESS is 1 I would like to silence that first warning line saying that depend.mk doesn't exist. I know it doesn't exist since I have a rule written to generate it, so the warning is unnecessary (unless of course there

Is there any way to get GNU make to print a "backtrace" of the targets that led to the command being executed when it fails? I regularly deal with heavily obfuscated makefiles while resolving portability issues building software on a new system, and it seems like this should be an extremely simple thing for make to do that would greatly aid in debugging, but I can't find any way to request it. What I'd like to see is something like: gcc: error: ... make[2]: error: gcc ... make[2]: error building target bar make[2]: error building dependency bar for target foo make[1]: error: make -C subdir

I have like this in makefile target1: export var1=test $(MAKE) target2 target2: echo $(var1) This is coming as empty I have other depencies so i want to set variable in first target and then all children dependencies should be able to access that EDIT: .ONESHELL: target1: export var1=test echo $(var1) output make target1 export var1=test echo By default make invokes a new shell environment for each recipe, the export ed variable on the first line isn't in scope for the second. You can fix this in multiple ways: Export the variable with make's export directive target1: export var1 := test

I have written a makefile like this: HEADER = -I./cygdrive/c/cpros/kajj/source4 LIBB = -L./cygdrive/c/cpros/kajj/source1 -L./cygdrive/c/cpros/kajj/source2 LIBRA = -larith -ldekk target : game.o gcc $(HEADER) $(LIBB) $< -o $@ $(LIBRA) game.o : game.c gcc -c game.c I have created my own static library and included the header file path and library path. When I execute my makefile it gives an error saying that /usr/lib/gcc cannot find -larith -ldekk . It is pointing to the lib/ directory but it is not over there: -ldekk and -larith are in source1 and source2 files respectively. How to solve this

I have some ancillary targets in a makefile that I want to restrict for internal or "private" use (only) inside the makefile. That is, I want to be able to specify these targets as dependencies from within the makefile, but I want to prevent the target from being specified as a build goal from the command line. Somewhat analogous to a private function from OOP: the target is harmful (or simply doesn't make sense) to build separately. I wish there were a special-target .HIDDEN or .PRIVATE or something that did this, akin to what .PHONY does for non-file targets, but I don't think this exists.

While using GNU-make, my Makefile has some pattern rule as: %.o:%.c gcc $< -o:$@ This rule is added by me. But when I do make it gives an error saying No rule to make target %.o and doesn't build the targets. At times, there is this other behaviour as well. It does not build the target when I say make first time(It gives error saying No rule to make target), but when i say make again immediately, it does build correctly. So when i explicity specify each source file separately, then it builds the targets fine first time itself. EDIT: I am using GNU-make on a Centos (v6.3 i guess, not sure).