gnu-make

I have a tool which generates multiple output files, which is notoriously hard to model in make. I'm using the recipe at GNU Makefile rule generating a few targets from a single source file , which seems simple and reliable. And it almost works. Unfortunately, I'm seeing some very odd behaviour with regard to parallel builds, where it seems to be dropping dependencies sometimes; and I don't understand why. Here's my test case: out3: out1 out2 touch out3 .INTERMEDIATE: out.intermediate out1 out2: out.intermediate out.intermediate: in touch out1 out2 If I build it once, it works: $ touch in $

Assume the following files are in the same directory as the makefile: 01.1.dot 01.2.dot 02.1.dot 03.1.dot 03.2.dot 03.3.dot That means we have files of the form [0-9][0-9].[0-9].dot Furthermore, the makefile contains the following target: %.dot.tex: %.dot dot2tex <...> Now I would like to create a target which depend on files of the form [0-9][0-9].tex and they should also depend on all files of the form [0-9][0-9].*.dot.tex, such that the first two digits match. For example, make 03.pdf should depend on 03.tex , 03.1.dot.tex , 03.2.dot.tex and 03.3.dot.tex . I came up with the following: %

I have a few software projects which are distributed as RPMs. They are versioned using semantic versioning to which we affix a release number . Using the regular conventions, this is MAJOR.MINOR.PATCH-REL_NUM . Though beyond the scope of this article, the release numbers are stored in git. The release target in the makefile looks something like this: release: make clean $(BLD_ROOT)/tools/incr_rel_num # Although the third step, this was re-ordered to step 1 $(eval RELEASE_NUMBER=$(shell cat $(BLD_ROOT)/path/to/rel_num.txt)) make rpm RPM_RELEASE_NUM=$(RELEASE_NUMBER) While debugging, I

My directory contains 2 source files: a.c and b.c . I want to generate executable file a from a.c and b from b.c . Now I can only figure out one method to write Makefile: all: gcc -o a a.c gcc -o b b.c It seems a little awkward, is it better method? The answers are fine, still I think you need some insight in how make works: The basic functionality of make is to create output files from input files if necessary . make decides what is necessary by comparing timestamps: If any input file is newer than an output file created from it, the recipe for this output file is executed. This means with

I'm trying to 'make' using a pretty simple makefile. My makefile is named 'Makefile' so I'm simply using the command 'make'. I get this strange error: make: *** No rule to make target `/Makefile', needed by `Makefile'. Stop. If, however, I use make -f "full-path-to-makefile" it actually does run (with odd consequences...). I should say that I'm running all this from the directory where the Makefile lies, of course. I'm working on Mac OSX, using tcsh. Edit: I'm working in the LLVM framework, trying to compile a pass function and this is the associated makefile: LEVEL = ../../../ LIBRARYNAME =