gnu-make

The current Makefile has something like this: target1 : lib1.a lib2.a target2 : lib1.a lib3.a target3 : lib3.a lib1.a: $(MAKE) -C sub_dir all I want to change this Makefile so that wherever a target depends on lib1.a , it always run the command " $(MAKE) -C sub_dir all ", always. Another words, in the above example, target1 and target2 will always run " $(MAKE) -C sub_dir all ". Is there any way I can do that? I know the following does not work: target1 : lib2.a $(MAKE) -C sub_dir all target2 : lib3.a $(MAKE) -C sub_dir all target3 : lib3.a Because if lib2.a has no update, the the command does

I want to autodetect system architecture, when i compile my program under freebsd and i want 2 includes for x64 and x32 but don't work, i tried like this : ifeq ($(uname -a),i386) INCDIR += -I../../x32 else INCDIR += -I../../x64 endif What is wrong here? When i compile on amd64 work with code below. When i compile on i388 don't work. When i compile on amd64 with code below the makefile see x64 dir. When i compile on i386 with code below the makefile see x64 dir. Soo bassicaly that else don't have any effect ? In GNU make syntax $() dereferences a variable. You rather want a shell command:

In the makefile of a program, one has to write rules that define the dependencies of each object file. Consider the object file fileA.o . It is obvious that this object file depends on the source file fileA.c . But it will also depend on all the header files that this source file includes. So the following rule should be added to the makefile: # This rule states that fileA.o depends on fileA.c (obviously), but also # on the header files fileA.h, fileB.h and fileC.h fileA.o: fileA.c fileA.h fileB.h fileC.h Note that the rule has no recipe. One could add a recipe to it, but it is strictly

So I have a makefile with a target dependency like this: all: $(foreach lang, $(LANGS), $(foreach models,$(MODELS),targetName$(model).xml$(lang))) and the targetName target looks like this: targetName%.xml%: MODEL\=% targetName.xml* But it doesn't work. I get this error: make[1]: *** No rule to make target `targetNameMYMODEL.xmlen', needed by `all'. Stop. however, calling 'all' with a hardcoded language in the targetName target like this works: all: $(foreach lang, $(LANGS), $(foreach models,$(MODELS),targetName$(model).xmlen)) and calling 'all' without the language in either all or targetName

I'm working on some bare-metal embedded code that runs on ARM, and thus has to deal with the whole ARM vs. THUMB mode distinction. The current build system uses static pattern rules to determine whether to compile files in ARM or THUMB mode. $(ACOBJS) : %.o : %.c @echo $(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $@ $(TCOBJS) : %.o : %.c @echo $(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $@ Where ACOBJS is a list of output objects that should be in ARM mode and the same for TCOBJS and Thumb mode. These lists are created from the list of sources in the usual manner of ACOBJS = $(ACSRC:

I have two makefiles, for native and cross compilation. The only difference between them is compiler name: # makefile CC = g++ ... # makefile-cc CC = arm-linux-gnueabihf-g++ ... To make native compilation, I execute make , to make cross-compilation, I execute make -f makefile-cc . I want to have one makefile , which should be executed using make for native compilation, and make cross for cross-compilation. What is correct syntax to do this, something like: # makefile (C-like pseudo-code) if cross CC = arm-linux-gnueabihf-g++ else CC = g++ You can assign/append variables for specific targets by

I have a makefile like the following: m1: @echo building m1 m1_: @echo building m1_ m2: @echo building m2 m2_: @echo building m2_ m3_DEPS = m2 m1 SUBSTITUTE=$(patsubst %,%_,$($@_DEPS)) .SECONDEXPANSION: #%: $$(SUBSTITUTE) %: $$(patsubst \%,\%_,$$($$@_DEPS)) @echo Building $@ @echo Dependencies are $^ The key line is %: $$(patsubst \%,\%_,$$($$@_DEPS)) I am using both a pattern rule and patsubst, which itself uses percentage signs. I thought I could escape the % character with a \ , but I am still not getting the expected behaviour. Running "make m3" gives the output building m2 building m1

I want to write something like regex: SRC:="a.dat.1 a.dat.2" $(SRC): %.dat.%: (\\1).rlt.(\\2) dat2rlt $^ $@ so that a.dat.1 and a.dat.2 will give a.rlt.1 and a.rlt.2 . In GNU Make info page, it says "the % can be used only once". Is there some trick to achieve this in GNU Make? I'm afraid what you are trying to do is not possible the way you suggest to do it, since - as you already mention - (GNU) make only allows a single stem '%', see http://www.gnu.org/software/make/manual/make.html#Pattern-Rules : A pattern rule looks like an ordinary rule, except that its target contains the character ‘%’

Closed . This question is opinion-based . It is not currently accepting answers. Want to improve this question? Update the question so it can be answered with facts and citations by editing this post . Closed last year . Assume the directory of a project contains subdirectories such as src , bin , lib , doc , etc. Where do I put the makefile of a project? For example, some projects put their makefile in src/ subdirectory of the root directories of the projects, some projects put their makefiles in the root directory of the project. The second way feels more logically organized to me. Can you