gnu-make

Assume 1000 files with extension .xhtml are in directory input, and that a certain subset of those files (with output paths in $(FILES), say) need to be transformed via xslt to files with the same name in directory output. A simple make rule would be: $(FILES): output/%.xhtml : input/%.xhtml saxon s:$< o:$@ foo.xslt This works, of course, doing the transform one file at a time. The problem is that I want to use saxon's batch processing to do all the files at one time, since, given the number of files, that would be much faster, considering the overhead of loading java and saxon for each file.

I have a function in a makefile that I want to stop the entire make run if a file doesn't exist, or at least the target it is executed from: vaultfile = ./vault $(shell test -f $(1) || exit 1) define get_token $(shell test -f $1 && cat $1 || exit 2) endef a: token = $(call get_token,$(vaultfile),tokenname) a: echo ==== $(token) .PHONY=a The above doesn't work, silently failing when the file is missing $ rm vault $ make echo ==== ==== $ echo f > vault $ make echo ==== f ==== f I want this to be in the function, because most targets do not call the function (which obviously does more IRL). How

A common problem I've seen with Makefiles is that executables (and libraries, for that matter) aren't necessarily relinked when the list of dependencies changes. For example: SRCS=$(wildcard *.c) CPPFLAGS=-MMD -MP target: $(SRCS:.c=.o) $(CC) $(LDFLAGS) $^ -o $@ -include $(SRCS:.c=.d) So far, so good: it automatically handles any changes to source files and their included dependencies. If a file is added (because of the wildcard, that means just adding it to the directory, but an explicit list would have the same problem), make sees it and relinks the target. However, when a source file is

I have a master makefile, which contains generic settings, and a child makefile that has project specific settings. From my other question about overriding variables in a makefile , I learned that I can use the following code in my master makefile: CC ?= avr-gcc CXX ?= avr-g++ In the child makefile, I use colorgcc and override these variables: CC ?= color-avr-gcc CXX ?= color-avr-g++ Everything works. But, if I remove the above lines from my child makefile, make starts using gcc and g++ instead of avr-gcc and avr-g++ . I guess both CC and CXX are treated differently and they are provided with

At the top of my Makefile, before any of the rules, I have the following: ifeq ($(ENVIRONMENT),LOCAL) TARGET := local_target else TARGET := hello endif If the ENVIRONMENT environment variable is not set, or is set to a value other than LOCAL , instead of setting TARGET to hello , I want the makefile to halt and exit with -1. Can I do that?? When I change TARGET := hello to exit -1 , I get the following error: Makefile:4: *** missing separator. Stop. How can I make this work?? exit is a shell command, so you could use the shell assignment operator (i.e.: != ) inside the Makefile to call exit :

I have a gnu Makefile that collects version information through environment variables. Now, I want to do "something" globally before any target is built using the gnumake syntax. As pseudo code, this means: when a specified file exists, delete it run through an array of strings and put their value into a specified file I tried this: $(shell if exist $(subst /,\,$(products)filenames.h) del /F/Q $(subst /,\,$(products)filenames.h)) $(foreach Item, $(EnvFilenames), @echo $(Item) >> $(subst /,\,$(products)filenames.h)) this gives me an error: C:\temp\Makefile.mak:72: *** missing separator. Stop.