gnu-make | 易学教程

How to run some commands globally in a Gnu Make file

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问题 I have a gnu Makefile that collects version information through environment variables. Now, I want to do "something" globally before any target is built using the gnumake syntax. As pseudo code, this means: when a specified file exists, delete it run through an array of strings and put their value into a specified file I tried this: $(shell if exist $(subst /,\,$(products)filenames.h) del /F/Q $(subst /,\,$(products)filenames.h)) $(foreach Item, $(EnvFilenames), @echo $(Item) >> $(subst /,\,$

When should a call to eval be evaluated in a make recipe

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问题 I have a few software projects which are distributed as RPMs. They are versioned using semantic versioning to which we affix a release number . Using the regular conventions, this is MAJOR.MINOR.PATCH-REL_NUM . Though beyond the scope of this article, the release numbers are stored in git. The release target in the makefile looks something like this: release: make clean $(BLD_ROOT)/tools/incr_rel_num # Although the third step, this was re-ordered to step 1 $(eval RELEASE_NUMBER=$(shell cat $

Setting PATH within Makefile on Mac OS X (but it works on Linux)

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I'm able to set PATH in a Makefile on Linux but not Mac OS X. With OS X, the PATH gets set but doesn't get used. Here's a demonstration: On CentOS 6 with bash 4.1.2(1)-release and GNU Make 3.81 $ pwd /tmp/experiment $ find * -type f -ls 132133 4 -rw-rw-r-- 1 tlim tlim 113 Aug 26 11:01 Makefile 132132 4 -rwxrwxr-x 1 tlim tlim 28 Aug 26 10:59 bin/myprog $ cat Makefile export PATH := $(shell /bin/pwd)/bin:$(PATH) what: @echo PATH=$$PATH @echo PATH=$(PATH) which myprog myprog $ cat bin/myprog #!/bin/bash echo HERE I AM. $ make what PATH=/tmp/experiment/bin:/usr/stack/bin:/usr/lib64/qt-3.3/bin:/usr

Non-recursive make: include makefile segment in a loop

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问题 I have a non recursive makefile which defines helper functions which can be used to build libraries etc define make-library # build lib from *.cpp in current dir... endef Each library/binary is defined in a separate makefile segment called module.mk which calls these helper functions $(eval $(call make-library, my_lib)) The makefile searches the source tree for makefile segments, and includes them modules := $(shell find . -name module.mk | xargs echo) include $(modules) Problem: I define a

GNU Makefile, detect architecture

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问题 I want to autodetect system architecture, when i compile my program under freebsd and i want 2 includes for x64 and x32 but don't work, i tried like this : ifeq ($(uname -a),i386) INCDIR += -I../../x32 else INCDIR += -I../../x64 endif What is wrong here? When i compile on amd64 work with code below. When i compile on i388 don't work. When i compile on amd64 with code below the makefile see x64 dir. When i compile on i386 with code below the makefile see x64 dir. Soo bassicaly that else don't

About the GNU make dependency files *.d

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问题 In the makefile of a program, one has to write rules that define the dependencies of each object file. Consider the object file fileA.o . It is obvious that this object file depends on the source file fileA.c . But it will also depend on all the header files that this source file includes. So the following rule should be added to the makefile: # This rule states that fileA.o depends on fileA.c (obviously), but also # on the header files fileA.h, fileB.h and fileC.h fileA.o: fileA.c fileA.h

How to follow linking order when linking against static library with gnu-make?

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问题 I've got the following problem: cc -g -O2 -Wall -Wextra -Isrc -rdynamic -DNDEBUG build/liblcthw.a tests/list_tests.c -o tests/list_tests /tmp/ccpvGjZp.o: In function `test_create': ~/lcthw/tests/list_tests.c:12: undefined reference to `List_create' collect2: ld returned 1 exit status make: *** [tests/list_tests] Error 1 But cc -g -O2 -Wall -Wextra -Isrc -rdynamic -DNDEBUG tests/list_tests.c build/liblcthw.a -o tests/list_tests runs just fine, nm shows the expected content, tests run,

One makefile for two compilers

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问题 I have two makefiles, for native and cross compilation. The only difference between them is compiler name: # makefile CC = g++ ... # makefile-cc CC = arm-linux-gnueabihf-g++ ... To make native compilation, I execute make , to make cross-compilation, I execute make -f makefile-cc . I want to have one makefile , which should be executed using make for native compilation, and make cross for cross-compilation. What is correct syntax to do this, something like: # makefile (C-like pseudo-code) if

How to correctly escape “%” sign when using pattern rules and patsubst in GNU make?

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问题 I have a makefile like the following: m1: @echo building m1 m1_: @echo building m1_ m2: @echo building m2 m2_: @echo building m2_ m3_DEPS = m2 m1 SUBSTITUTE=$(patsubst %,%_,$($@_DEPS)) .SECONDEXPANSION: #%: $$(SUBSTITUTE) %: $$(patsubst \%,\%_,$$($$@_DEPS)) @echo Building $@ @echo Dependencies are $^ The key line is %: $$(patsubst \%,\%_,$$($$@_DEPS)) I am using both a pattern rule and patsubst, which itself uses percentage signs. I thought I could escape the % character with a \ , but I am

Automake Variables to tidy up Makefile.am

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问题 I have a directory /src containing all of my source files, and /bin to store all binary after running make command. The directory is something like below: /BuildDirectory - - /src - - /bin - - configure - - Makefile.am - - configure.ac - - ... Now in Makefile.am, I have to specified: bin_PROGRAMS = bin/x bin/y bin/z bin/k ... bin_x_SOURCES = src/x.cpp bin_y_SOURCES = src/y.cpp bin_z_SOURCES = src/z.cpp Is there any variable that can help to get rid of all "bin/" and "src/" ? For example I