VHDL - Assigning Default Values
问题 I have the following architecture: architecture datapath of DE2_TOP is begin U1: entity work.lab1 port map ( --error on this line clock => clock_50, key => key, hex6 => hex6, hex5 => hex5, hex4 => hex4 ); end datapath; This architecture obviously depends on lab1 entity. Here is my lab1 entity and architecture: entity lab1 is port( clock : in std_logic; key : in std_logic_vector(3 downto 0); hex4, hex5, hex6 : out std_logic_vector(6 downto 0); value_counter : in unsigned(7 downto 0); register