VHDL - Assigning Default Values

问题

I have the following architecture:

architecture datapath of DE2_TOP is

begin
  U1: entity work.lab1 port map ( --error on this line
    clock => clock_50,
    key => key,
    hex6 => hex6,
    hex5 => hex5,
    hex4 => hex4
  );

end datapath;

This architecture obviously depends on lab1 entity. Here is my lab1 entity and architecture:

entity lab1 is
    port(
        clock : in std_logic;
        key : in std_logic_vector(3 downto 0);
        hex4, hex5, hex6 : out std_logic_vector(6 downto 0);
        value_counter   : in unsigned(7 downto 0);
        register_counter : in unsigned(3 downto 0)
        );
end lab1;

architecture up_and_down of lab1 is
    signal hex5_value : unsigned(7 downto 0);
        begin
    process(clock)
        begin
            value_counter<="00000000"; --default values?
            register_counter<="0000";
            if rising_edge(clock) then
                if (key(3)='0' and key(2)='0' and key(1)='1' and key(0)='0') then
                    value_counter <= value_counter + "1";   
                elsif (key(3)='0' and key(2)='0' and key(1)='0' and key(0)='1') then  
                    value_counter <= value_counter - "1";   
                end if;
            end if;
            hex5_value <= (value_counter - (value_counter mod 10))/10;
    end process;

end architecture up_and_down;

I am getting the following error: Error (10346): VHDL error at DE2_TOP.vhd(280): formal port or parameter "value_counter" must have actual or default value on the indicated line. It seems to me that I have set the default values already in my lab1 architecture. Anyone know what the problem is?

回答1:

That's not a "default value" but an assignment to initialise it. It's also assigning to an input port which is illegal. Also, the entity is compiled before the architecture so the (illegal) assignment doesn't exist yet.

signal value_counter : unsigned(7 downto 0) := (others => 'X');

is a default value (or initial value), supplied in the declaration

port (
   value_counter   : in unsigned(7 downto 0) := (others => '1');

would be a default value on an input port, but I've never seen that done. I've always connected all input ports in the port map. If this works I'm (slightly) impressed, but probably not enough to be happy about unconnected inputs; it seems too easy to overlook mistakes that way.

回答2:

You are not driving anything onto the value_counter input. All entity inputs must have either a signal driving them, or a default value specified in the entity declaration.

The latter is useful for inputs which are optional:

entity lab1 is
    port(
        clock : in std_logic;
        key : in std_logic_vector(3 downto 0);
        hex4, hex5, hex6 : out std_logic_vector(6 downto 0);
        value_counter   : in unsigned(7 downto 0) := (others => '-');
        register_counter : in unsigned(3 downto 0)
        );
end lab1;

will ensure that value_counter gets don't care bits (-) assigned to it if you don't wire it up. Or if you could like it to be all zeros,

        value_counter   : in unsigned(7 downto 0) := (others => '0');

来源：https://stackoverflow.com/questions/14527201/vhdl-assigning-default-values

标签

compiler-errors

default-value

vhdl