cpu-registers

What happens to registers when you manipulate them using asm code in C++?

我是研究僧i 提交于 2021-02-20 03:00:07
问题 Some code: int x = 1; for(int i = 1; i < 10; i++) { x *= i; __asm { mov eax, x }; } If this program uses eax in order to increase the value of i , what will happen when I manipulate eax ? Will the compiler save registers from before the __asm call and use them after the asm code was executed or will it ignore that eax was manipulated and continue producing some sort of strange behavior? What happens to eax internally? EDIT: Even if my code only works with Visual C++ I want to know what

What happens to registers when you manipulate them using asm code in C++?

北城余情 提交于 2021-02-20 03:00:07
问题 Some code: int x = 1; for(int i = 1; i < 10; i++) { x *= i; __asm { mov eax, x }; } If this program uses eax in order to increase the value of i , what will happen when I manipulate eax ? Will the compiler save registers from before the __asm call and use them after the asm code was executed or will it ignore that eax was manipulated and continue producing some sort of strange behavior? What happens to eax internally? EDIT: Even if my code only works with Visual C++ I want to know what

Get userspace RBP register from kernel syscall

孤者浪人 提交于 2021-02-11 15:01:31
问题 I am writing a kernel system call and I want to read the base pointer register (RBP) of the user. Maybe I can do that using the pt_regs struct that is passed for parameter, isn't it? Example code: unsigned long int data; asmlinkage int my_read(int d) { get_rbp_of_userStack(&data);#or somthing like that } I know this data saved somewhere for the context switch, how can I get to it? this is my user code void rar() {//rbp here should be rsp when it call so it basically the return addres of the

ABI Register Names for RISC-V Calling Convention

落爺英雄遲暮 提交于 2021-02-08 12:19:40
问题 I'm confused about the RISC-V ABI Register Names. For example, Table 18.2 in the "RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0" at page 85 specifies that the stack pointer sp is register x14 . However, the instruction addi sp,zero,0 is compiled to 0x00000113 by riscv64-unknown-elf-as ( -m32 does not make a difference). In binary: 000000000000 00000 000 00010 0010011 ^imm ^rs1 ^f3 ^rd ^opcode So here sp seems to be x2 . Then I googled a bit and found the RISC-V Linux

Difference between memory and register

不羁的心 提交于 2021-02-07 04:35:13
问题 I saw assembly code like, MOV [EAX], EBX the above line, They are mentioned [EAX] is memory and EBX is Register. So, here what is the difference between [EAX] and EBX . What will happen in above instruction. 回答1: In this syntax, brackets around a register means a memory location is used (as source or destination, according to the instruction) with starting address specified at the register (EAX in your case). For example, if EAX contained 1344 before the instruction, value from EBX is copied

Why use RIP-relative addressing in NASM?

生来就可爱ヽ(ⅴ<●) 提交于 2021-02-06 09:25:50
问题 I have an assembly hello world program for Mac OS X that looks like this: global _main section .text _main: mov rax, 0x2000004 mov rdi, 1 lea rsi, [rel msg] mov rdx, msg.len syscall mov rax, 0x2000001 mov rdi, 0 syscall section .data msg: db "Hello, World!", 10 .len: equ $ - msg I was wondering about the line lea rsi, [rel msg] . Why does NASM force me to do that? As I understand it, msg is just a pointer to some data in the executable and doing mov rsi, msg would put that address into rsi .

MMX Register Speed vs Stack for Unsigned Integer Storage

时光怂恿深爱的人放手 提交于 2021-02-05 08:56:49
问题 I am contemplating an implementation of SHA3 in pure assembly. SHA3 has an internal state of 17 64 bit unsigned integers, but because of the transformations it uses, the best case could be achieved if I had 44 such integers available in the registers. Plus one scratch register possibly. In such a case, I would be able to do the entire transform in the registers. But this is unrealistic, and optimisation is possible all the way down to even just a few registers. Still, more is potentially

Why floating point registers are different than general purpose ones

筅森魡賤 提交于 2021-02-05 07:13:25
问题 Most architectures have different set of registers for storing regular integers and floating points. From a binary storage point of view, it shouldn't matter where things are stored right? it's just 1's and 0's, couldn't they pipe the same general purpose registers into floating point ALUs? SIMD ( xmm in x64) registers are capable of storing both Floating point and regular integers, so why doesn't the same concept apply to regular registers? 回答1: For practical processor design, there are a

Can an x86 CPU read the value of any register while in user mode?

為{幸葍}努か 提交于 2021-02-05 06:54:05
问题 I have read that there are some registers that an x86 CPU cannot modify while in user mode (I believe these registers are called "privileged registers"). But can an x86 CPU read the values of these registers while in user mode, or is even reading not allowed? 回答1: All the registers you'd normally use for computation can be read/written in any mode (GP integer, x87/MMX, XMM/YMM/ZMM and AVX512 k0-7 mask registers), but there are many registers that are basically mode/control settings. Some

How do I interpret the columns of the CPU window's disassembly pane?

十年热恋 提交于 2021-02-04 16:19:41
问题 There is a tool called the CPU window, which I get pressing Ctrl + Alt + C , that shows the disassembly of my code. A green arrow to the left of the memory address indicates the location of the current execution point, then there is the memory addresses, but what does the second column mean, and why does the compiler sometimes jump more than one address after an instruction? For example: |first column|second column|assembly| 004520F4 55 push ebp //continuous 004520F5 8BEC mov ebp, esp //jumps