cpu-registers

问题 There is a tool called the CPU window, which I get pressing Ctrl + Alt + C , that shows the disassembly of my code. A green arrow to the left of the memory address indicates the location of the current execution point, then there is the memory addresses, but what does the second column mean, and why does the compiler sometimes jump more than one address after an instruction? For example: |first column|second column|assembly| 004520F4 55 push ebp //continuous 004520F5 8BEC mov ebp, esp //jumps

问题 After looking at a table of registers in the x86/x64 architecture, I noticed that there's a whole section of 128, 256, and 512-bit registers that I've never seen them being used in assembly, or decompiled C/C++ code: XMM(0-15) for 128, YMM(0-15) for 256, ZMM(0-31) 512. After doing a bit of digging what I've gathered is that you have to use 2 64 bit operations in order to perform math on a 128 bit number, instead of using generic add , sub , mul , div operations. If this is the case, then what

问题 After looking at a table of registers in the x86/x64 architecture, I noticed that there's a whole section of 128, 256, and 512-bit registers that I've never seen them being used in assembly, or decompiled C/C++ code: XMM(0-15) for 128, YMM(0-15) for 256, ZMM(0-31) 512. After doing a bit of digging what I've gathered is that you have to use 2 64 bit operations in order to perform math on a 128 bit number, instead of using generic add , sub , mul , div operations. If this is the case, then what

问题 After looking at a table of registers in the x86/x64 architecture, I noticed that there's a whole section of 128, 256, and 512-bit registers that I've never seen them being used in assembly, or decompiled C/C++ code: XMM(0-15) for 128, YMM(0-15) for 256, ZMM(0-31) 512. After doing a bit of digging what I've gathered is that you have to use 2 64 bit operations in order to perform math on a 128 bit number, instead of using generic add , sub , mul , div operations. If this is the case, then what

问题 After looking at a table of registers in the x86/x64 architecture, I noticed that there's a whole section of 128, 256, and 512-bit registers that I've never seen them being used in assembly, or decompiled C/C++ code: XMM(0-15) for 128, YMM(0-15) for 256, ZMM(0-31) 512. After doing a bit of digging what I've gathered is that you have to use 2 64 bit operations in order to perform math on a 128 bit number, instead of using generic add , sub , mul , div operations. If this is the case, then what

问题 After looking at a table of registers in the x86/x64 architecture, I noticed that there's a whole section of 128, 256, and 512-bit registers that I've never seen them being used in assembly, or decompiled C/C++ code: XMM(0-15) for 128, YMM(0-15) for 256, ZMM(0-31) 512. After doing a bit of digging what I've gathered is that you have to use 2 64 bit operations in order to perform math on a 128 bit number, instead of using generic add , sub , mul , div operations. If this is the case, then what

问题 Closed . This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this post. Closed 6 years ago . Improve this question I've been trying to learn everything I can about micro-controllers lately. Since this is self-study, it's taken me a while to learn how the things work at the bare metal. Long story short, I don't want to use the AVR libraries in my C code; I want to access

问题 In what I've learned so far about segmentation: A virtual address contains a segment selector and an offset The segment selector is used in conjunction with the GDTR to find the linear address of the segment descriptor The segment descriptor houses information regarding the chosen segment, including its linear address So, my questions are: Based on what I've read, the virtual address is loaded into the segment register, and then somehow the translation is continued from there. What happens to

问题 Closed . This question needs to be more focused. It is not currently accepting answers. Want to improve this question? Update the question so it focuses on one problem only by editing this post. Closed 4 years ago . Improve this question I would like to directly read the minimum temperate at which the TCC will be activated from the TEMPERATURE_TARGET register in my Intel i7-5930k. The Socket Thermal Guide (http://www.intel.com/content/www/us/en/processors/core/core-i7-lga2011-3-tmsdg.html)

问题 Hey I am having hard time solving my homework. Then x86 processor executes commands EIP register(counter) value increases by 1 byte or by a few bytes depending on command's type. Which instructions we have to use so EIP value may go over 100 bytes? Answers are: JMP | ADD | SUB | PUSH | JNZ | MUL | CALL | JZ As I get the idea, EIP is special case register which we can't use. It's called Extended Instruction Pointer. And to increase it's value over 100 bytes, we need to find how much each