cpu-cache

The Intel core i7 has per-core L1 and L2 caches, and a large shared L3 cache. I need to know what kind of an interconnect connects the multiple L2s to the single L3. I am a student, and need to write a rough behavioral model of the cache subsystem. Is it a crossbar? A single bus? a ring? The references I came across mention structural details of the caches, but none of them mention what kind of on-chip interconnect exists. Thanks, -neha Modern i7's use a ring. From Tom's Hardware : Earlier this year, I had the chance to talk to Sailesh Kottapalli, a senior principle engineer at Intel, who

Assume there are two threads running on x86 CPU0 and CPU1 respectively. Thread running on CPU0 executes the following commands: A=1 B=1 Cache line containing A initially owned by CPU1 and that containing B owned by CPU0. I have two questions: If I understand correctly, both stores will be put into CPU’s store buffer. However, for the first store A=1 the cache of CPU1 must be invalidated while the second store B=1 can be flushed immediately since CPU0 owns the cache line containing it. I know that x86 CPU respects store orders. Does that mean that B=1 will not be written to the cache before A=1

I've seen there is a plenty of them. NCache, Velocity and so forth but I haven't found a table comparing them. What's the best considering the following criterias: Easy to understand. Is being maintained lately. Is free or has a good enough free version. Works. I can't speak for what's best or worst, but I'll throw in my experience with NCache in case it helps. Disclaimer: NHibernate and I had some disagreements, we have since gone our separate ways :) The Good The performance was great The support was great, it's well maintained (I'm speaking to status as of ~6 months ago) It has a free

Every modern high-performance CPU of the x86/x86_64 architecture has some hierarchy of data caches: L1, L2, and sometimes L3 (and L4 in very rare cases), and data loaded from/to main RAM is cached in some of them. Sometimes the programmer may want some data to not be cached in some or all cache levels (for example, when wanting to memset 16 GB of RAM and keep some data still in the cache): there are some non-temporal (NT) instructions for this like MOVNTDQA ( https://stackoverflow.com/a/37092 http://lwn.net/Articles/255364/ ) But is there a programmatic way (for some AMD or Intel CPU families

The x86 INVD invalidates the cache hierarchy without writing the contents back to memory, apparently. I'm curious, what use is such an instruction? Given how one has very little control over what data may be in the various cache levels and even less control over what may have already been flushed asynchronously, it seems to be little more than a way to make sure you just don't know what data is held in memory anymore. Excellent question! One use-case for such a blunt-acting instruction as invd is in specialized or very-early-bootstrap code, such as when the presence or absence of RAM has not

When a cache miss occurs, the CPU fetches a whole cache line from main memory into the cache hierarchy. (typically 64 bytes on x86_64) This is done via a data bus, which is only 8 byte wide on modern 64 bit systems. (since the word size is 8 byte) EDIT: "Data bus" means the bus between the CPU die and the DRAM modules in this context. This data bus width does not necessarily correlate with the word size. Depending on the strategy the actually requested address gets fetched at first, and then the rest of the cache line gets fetched sequentially. It would seem much faster if there was a bus with

From the 11th Chapter( Performance and Scalability ) and the section named Context Switching of the JCIP book : When a new thread is switched in, the data it needs is unlikely to be in the local processor cache, so a context-switch causes a flurry of cache misses, and thus threads run a little more slowly when they are first scheduled. Can someone explain in an easy to understand way the concept of cache miss and its probable opposite ( cache hit )? Why context-switching would cause a lot of cache miss? Can someone explain in an easy to understand way the concept of cache miss and its probable