cpu-cache

(a) You are given a memory system that has two levels of cache (L1 and L2). Following are the specifications: Hit time of L1 cache: 2 clock cycles Hit rate of L1 cache: 92% Miss penalty to L2 cache (hit time of L2): 8 clock cycles Hit rate of L2 cache: 86% Miss penalty to main memory: 37 clock cycles Assume for the moment that hit rate of main memory is 100%. Given a 2000 instruction program with 37% data transfer instructions (loads/stores), calculate the CPI (Clock Cycles per Instruction) for this scenario. For this part, I calculated it like this (am I doing this right?): (m1: miss rate of

Relation between cache size and page size How does the associativity and page size constrain the Cache size in virtually addressed cache architecture? Particularly I am looking for an example on the following statement: If C≤(page_size x associativity), the cache index bits come only from page offset (same in Virtual address and Physical address). Peter Cordes Intel CPUs have used 8-way associative 32kiB L1D with 64B lines for many years, for exactly this reason. Pages are 4k, so the page offset is 12 bits, exactly the same number of bits that make up the index and offset within a cache line.

The Intel Architectures Software Developer's Manual, Aug. 2012, vol. 3A, sect. 8.2.2: Any two stores are seen in a consistent order by processors other than those performing the stores. But can this be so? The reason I ask is this: Consider a dual-core Intel i7 processor with HyperThreading. According to the Manual's vol. 1, Fig. 2-8, the i7's logical processors 0 and 1 share an L1/L2 cache, but its logical processors 2 and 3 share a different L1/L2 cache -- whereas all the logical processors share a single L3 cache. Suppose that logical processors 0 and 2 -- which do not share an L1/L2 cache

Consider the diagrammed data cache architecture. (ASCII art follows.) -------------------------------------- | CPU core A | CPU core B | | |------------|------------| Devices | | Cache A1 | Cache B1 | with DMA | |-------------------------| | | Cache 2 | | |------------------------------------| | RAM | -------------------------------------- Suppose that an object is shadowed on a dirty line of Cache A1, an older version of the same object is shadowed on a clean line of Cache 2, and the newest version of the same object has recently been written to RAM via DMA. Diagram: -------------------------

I'm trying to understand direct mapped cache, but it is a very complex concept. I have written what I think I understand so far, but I am unsure whether I am correct or not. Can somebody please verify if the explanation below is correct? E.g, for a made up computer, just for the sake of this question, there 1024 memory locations (cells) in the RAM. This equals 2^10 so the address for each of these memory locations must be 10 bits long. The CPU is asked to get data from the RAM memory address 1100100111 . However the CPU doesn't access the data directly from this memory address in the RAM. The

A direct mapped cache consists of 16 blocks. main memory contains 16K blocks of 8 bytes each. What is the main memory address format (meaning the size of each field). I know the fields are Tag|Block|Offset . I just don't know how to get the sizes of each. Is this homework? In order to solve this problem, you'd need to know the address size of the architecture in question. General solution: Let C be the size of the cache in bits. Let A be the size of an address in bits. Let B be the size of a cache block in bits. Let S be the associativity of the cache (in ways, direct-mapped being S=1 and

Summary Consider the following loop: loop: movl $0x1,(%rax) add $0x40,%rax cmp %rdx,%rax jne loop where rax is initialized to the address of a buffer that is larger than the L3 cache size. Every iteration performs a store operation to the next cache line. I expect that the number of RFO requests sent from the L1D to the L2 to be more or less equal to the number of cache lines accessed. The problem is that this seems to be only the case when I count kernel-mode events even though the program runs in user-mode, except in one case as I discuss below. The way the buffer is allocated does not seem

This question already has an answer here: Are loads and stores the only instructions that gets reordered? 2 answers Which is a better write barrier on x86: lock+addl or xchgl? 5 answers Does lock xchg have the same behavior as mfence? 1 answer What is the difference in logic and performance between x86-instructions LOCK XCHG and MOV+MFENCE for doing a sequential-consistency store. (We ignore the load result of the XCHG ; compilers other than gcc use it for the store + memory barrier effect.) Is it true, that for sequential consistency, during the execution of an atomic operation: LOCK XCHG