circuit

An ArrowCircuit instance for stream processors which could block

半世苍凉 提交于 2021-01-21 07:30:30
问题 The Control.Arrow.Operations.ArrowCircuit class is for: An arrow type that can be used to interpret synchronous circuits. I want to know what synchronous means here. I looked it up on Wikipedia, where they are speaking of digital electronics. My electronics is quite rusty, so here is the question: what is wrong (if anything is) with such an instance for the so-called asynchronous stream processors: data StreamProcessor a b = Get (a -> StreamProcessor a b) | Put b (StreamProcessor a b) | Halt

Find the Shortest Cycle in Graph

断了今生、忘了曾经 提交于 2019-12-25 19:30:29
问题 I have a problem with finding cycles in graph. In the condition we have to find the shortest cycle in directed graph. My graph is (A,B,C,D) and the connections (arcs) between the elements are: (A->B), (A->A), (B->C), (B->A), (C->D), (C->A), (D->A) and so cycles are the following: А->B->C->D->A; A->B->C->A; A->B->A; A->A. Program should print the shortest cycle, ie A->A. To solve it i need first to find all cycles, then put them each in a separate list and finally bring the smallest list,

How to detect oscillations in gate logic simulations?

廉价感情. 提交于 2019-12-23 20:53:21
问题 I'm writing cycle based logic simulation in C#. I want to simulate both combinational and sequential circuits. Combinational circuits are straightforward but sequential circuits give me trouble. I want to detect oscillations and display appropriate warning message. Is there a simple way to check how many times a single gate can change its state and still leave the circuit stable? I thought about 'minimum feedback arc set algorithm' but it seems to be an overkill. Many desktop applications

How to handle loops in a digital logic simulator?

痞子三分冷 提交于 2019-12-23 09:22:40
问题 I'm developing a digital logic simulator to build my own CPU in it later (so it's a long term project). Everything works great for circuits with no loops, for example a fulladder. Then there are circuits like an SR latch, where one of the inputs of a gate is connected to the output of another gate. So I'm in a loop, because both gates need the output of the other one, to compute their own output. What is the best way to solve this? I implemented it in a way, that (when a loop is detected) it

I have a formlayout error when running a Blazor website

半腔热情 提交于 2019-12-23 06:41:43
问题 I updated visual studio 19 and before that my site ran exactly how i intended it. Now i am getting an error when i load the home page but then breaks before it can finish loading it. I have provided the error code below. I also would let you know that i have seen this post ( How to turn on CircuitOptions.DetailedErrors? ) and tried it all but it hasn't worked. Information: Normalizing '_blazor' to 'http://fakesite.com/_blazor'. Error: There was an unhandled exception on the current circuit,

Steps to make a LED blink from a C/C++ program?

戏子无情 提交于 2019-12-20 10:01:52
问题 What are the easiest steps to make a small circuit with an LED flash from a C/C++ program? I would prefer the least number of dependencies and packages needed. What port would I connect something into? Which compiler would I use? How do I send data to that port? Do I need to have a micro-processor? If not I don't want to use one for this simple project. EDIT: Interested in any OS specific solutions. 回答1: Here's a tutorial on doing it with a parallel port. Though I would recommend an Arduino

When should I use reg instead of wire? [duplicate]

瘦欲@ 提交于 2019-12-20 06:42:16
问题 This question already has answers here : Using wire or reg with input or output in Verilog (5 answers) Closed 3 years ago . I'm confused about reg and wire when I was doing my homework. I could not understand differences between reg and wire exactly. Can you explain shortly? Also, I wonder that what will happen when I use output q instead of output reg q ? 回答1: In simulation , a Verilog wire behaves like a piece of metal, a track, a wire, whilst a Verilog reg is a variable, it is storage*.

Should I eliminate inputs in a logic circuit design?

空扰寡人 提交于 2019-12-11 10:16:57
问题 Recently I had an exam where we were tested on logic circuits. I encountered something on that exam that I had never encountered before. Forgive me for I do not remember the exact problem given and we have not received our grade for it; however I will describe the problem. The problem had a 3 or 4 inputs. We were told to simplify then draw a logic circuit design for that simplification. However, when I simplified, I ended up eliminating the other inputs and ended up literally with just A I

Create Prolog Vocabulary

扶醉桌前 提交于 2019-12-11 02:39:47
问题 i am quite new to prolog, and i have some basic questions... I dont know if "vocabulary" is the right world in english, but i need to create one to describe an eletronic circuit. My problem is, how do i create these functions and how i use the "=" statement since prolog doesnt seems do acept it. Im using SWI Prolog. (tried my best to translate to english)Thats what i have to put in prolog: Decide the vocabulary (Predicates, functions, constants): Ports are represented by constants (X1, X2, ..

Precendence vs short-circuiting in C [closed]

元气小坏坏 提交于 2019-12-04 07:16:13
问题 It's difficult to tell what is being asked here. This question is ambiguous, vague, incomplete, overly broad, or rhetorical and cannot be reasonably answered in its current form. For help clarifying this question so that it can be reopened, visit the help center. Closed 7 years ago . int i=-3, j=2, k=0, m; m = ++i || ++j && ++k; printf("%d, %d, %d, %d\n", i, j, k, m); Since ++ has more precedence than || and && in C, they are evaluated first and therefore the expression becomes m = -2 || 3 &&