Verilog signed vs unsigned samples and first
问题 Assuming I have a register reg [15:0] my_reg , which contains a 16-bit signed sample: How do I convert the sample from signed to unsigned? I have read this Wikipedia article, and am aware of the 2-bit complement for signed numbers, but how do I perform this conversion in Verilog efficiently? (I don't know if my_reg is positive or negatve, and it changes in every clock cycle = I receive a new sample on every positive clock edge). The ultimate goal (to add a little bit of context) is to