xilinx

问题 I have never come across this problem before when uses black-boxes inside custom IP. Usually I instantiate and add the custom IP to the project, and then instantiate and add the black box IP modules (the black boxes are inside the custom IP) to the project. For some reason now I am getting the classic [Project 1-486] Could not resolve non-primitive black box cell 'FX_Thomas_Core_0FX_Thomas_Core_0FX_Thomas_Core_0Thomas_Sub' instantiated as 'Subtractor' ["c:/Users/Sam/Documents/Zynq7020/FX

问题 I have spent the whole day trying to solve the following problem. I am building a small averaging multichannel oscilloscope and I have the following module for storing the signal: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; entity storage is port ( clk_in : in std_logic; reset : in std_logic; element_in : in std_logic; data_in : in std_logic_vector(11 downto 0); addr : in std_logic_vector(9 downto 0); add : in std_logic; -- add = '1'

问题 The full error message is: ERROR:HDLCompiler:377 - "C:/Users/einar/Documents/Xilinx/ISE/Projects/EDA385/scale_clock_tb.vhd" Line 17: Entity port d does not match with type unsigned of component port I'm using ISE web pack and I have implemented the top module, the top module is scale_clock. Also, it simulates just fine when I do behavioral simulation. But for post-map or post-route I get the error message above. This is the code for the component: library IEEE; use IEEE.STD_LOGIC_1164.ALL;

问题 I am trying out programming my digilent FPGA through the vivado command line. After opening the hardware server I can program my device as follows... program_hw_devices [get_hw_devices xc7a100t_0] Then if I run puts [get_hw_devices xc7a100t_0] it outputs xc7a100t_0 which leads me to think that I should be able to just do something like program_hw_devices xc7a100t_0 . This however fails and I get the following output. ERROR: [Common 17-161] Invalid option value 'xc7a100t_0' specified for 'hw

问题 I am getting through the tutorial of Nexys 4 DDR and I am implementing a simple MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lab1_2_1 is Port ( SW0 : in

问题 In the following code: First, I am loading ROM with data and weight at given address. In the same clock I am doing multiplication of data and weight. Finally, I am extending the number of bits from 16-bit to 23-bit. The code compiles without errors but has warnings. I am unable to solve these warnings. module main_module(extended_out,mux_out,data,weight,clk,en,addr); input clk,en; input [2:0] addr; output [7:0] data,weight; output [15:0] mux_out; output [22:0] extended_out; ram_input a1 (clk,

问题 I am trying to convert the input word coming out of the DQPSK Demodulator (Type : UFix2_0) to a serial stream. So I am using the Parallel-to-Serial Block of Xilinx Library in Simulink. But I am not able to use the block, I get the following error : "The Simulink system period" setting on this System Generator token is not appropriate for the rates used in the design. The current setting is: 1 An appropriate setting is: 1/2 " I tried to change the setting the System Generator as well, but It

问题 I'm trying to implement a simple verilog code as below: module test1( input ACLK, input RST, output test_output1, output test_output2 ); //wire ACLK; //wire RST; reg test_output1; reg test_output2; assign test_output1 = ACLK; always @(posedge ACLK or negedge RST) begin if(!RST) begin //test_output1 <=0; test_output2 <=0; end else begin //test_output1 <=0; test_output2 <=1; end end endmodule I get the following error message when I try to synthesize it in Xilinx ISE: ==========================

问题 Referring to my earlier question here, I've been utilizing tri-states to work with a common bus. I still appear to have some implementation issues. The tri-states use this type of code: assign io [width-1:0] = (re)?rd_out [width-1:0]:{width{1'bz}}; Synthesis and translation goes well. No warnings or errors I wasn't expecting (I was expecting some since this is only a trial run and most of the components don't do anything and will hence be left unconnected). But when I actually try to