xilinx | 易学教程

How to compare integer values with binary in for loop for Delay Generation in Verilog Synthesis?

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问题 Hello Friends I still not know how to Generate Delay in Verilog For synthesis and call it any line in Verilog for synthesis...for finding this I write a code but it not works please help me if you know how to Generate Delay and call in any line like a C's Function* ......Actually Friends if you tell me why I use for Loop here then my answer is - I want to move pointer inside for loop until and unless they completes its calculation that I made for Delay Generation .. module state_delay; reg

Counter with push button switch design using VHDL and Xilinx

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问题 I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE. I want to design a very simple counter with the following inputs: Direction Count The count input will be assigned to a button and I want the counter to count up or down according to direction input when the button is pressed. I have written a sample VHDL before this one. It had a clock input and It was counting according to the clock input. Now I want it to count when I press the button instead of counting

Can Vivado handle user defined physical types?

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问题 I wrote some cross platform VHDL libraries for Xilinx XST, iSim, Altera Quartus II, Mentor Graphics QuestaSim and GHDL. Now I wanted to port my ISE 14.7 project, which uses these libraries to Vivado 2014.4, but one library seems to have fatal problems. My library physical defines several new user defined physical types like: FREQUENCY and BAUD ; conversion functions and report functions. One main use case is the calculation of delay or counter cycles for a given delay and system frequency. So

Xilinx FPGA的多重配置功能（2）

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转至 https://mp.weixin.qq.com/s?__biz=MzI4NjQzNTUyOA==&mid=2247484094&idx=1&sn=42f89e138dbbfb199a39b3a3e0d3e582&chksm=ebddb319dcaa3a0fb8f3033d17934d21b06d8676464d4b44d6c2c290dee9793ad25052630201&mpshare=1&scene=1&srcid=1228KALf10w5ebbHQzecmFXH ## 当我们在对产品的FPGA代码做远程升级时，通常都是把加密后的下载文件发给用户，让用户在本地进行下载升级。但有时候由于我们没检查好，致使更新程序有问题，这样给到用户手上下载后，就会使得东西无法工作或者工作异常。如果不是紧急情况，做些沟通再把正确的文件重新给用户即可；但如果设备是属于持续工作型，那便一个钟也耽误不起，此时便会造成很多不必要的麻烦了。所以在对FPGA代码进行远程升级时，建议使用多重配置功能。 1.ICAPE核使用多重配置功能时，必须调用FPGA内部的ICAPE核，该核可以对上一节讲的IPROG的指令进行配置。 IPROG配置指令在Vivado中的“Language Templates”中进行搜索，输入”ICAPE”便可以看到你所使用的器件对应的ICAPE核的源语了。ISE的也是如此。

What is it called the threads on the FPGA (Xilinx Virtex 5/7), and how many number of its can be?

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问题 What is it called the thread of execution on the FPGA (Xilinx Virtex 5/7), and how many number of its can be theoretically (minimum and maximum)? 回答1: FPGAs are reprogrammable circuits, and the components of those circuits are always running in parallel. The concept of threads from software development and multi-threaded processors do not apply to hardware design on an FPGA. If you define a "thread" as a unit of computation that can operate in parallel from other units, you could say an FPGA

Unexpected warnings in Xilinx

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问题 In the following code, I am storing the history of buttons player 1 and player 2 pressed. The code compiles without errors but has warnings. I am unable to solve these warnings. I am posting the code here. module game(clk50,red,green,blue,hsync,vsync, button,led); input [8:0] button; input clk50; output red; output green; output blue,led; output hsync; output vsync; // divide input clock by two, and use a global // clock buffer for the derived clock reg clk25_int; always @(posedge clk50)

VHDL XST not synthesizing correctly

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问题 I've been working on a packet sorting pipeline in VHDL using Xilinx ISE 14.2. In order to make the structure generic I wrote a few algorithms in a package that will determine how to connect sorting nodes. Interestingly when I design a test bench around the functions the results are correct. When I simulate my design in the project using a combination of generates and functions the hardware is wired correctly. (used 'assert false report " & integer'image(layer);' to validate in simulation)

Ways to implement recipricals on Verilog

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问题 I want to implement a reciprical block on Verilog that will later be synthesized on an FPGA. The input should be a signed 32 bit wordlength with a 16 bit fraction length. The output should have the same format. Example input : x ---> output ---> 1/x I have solved the problem using the inbuilt IP core divider. I'm wondering if there is an elegant/altenative way of solving this by for example by bit shifting or 2's complement with some xor grinds. I have used the IP core to implement the

Error in testbench

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问题 I'm a beginner to vhdl. I am trying to write a VHDL code to describe the behavior of a traffic light. It has 3 signal outputs Yellow (0), Green (1) and Red (2). Initially the light is yellow. It would be turning to Green after 10ns. Green would turn to red after 40ns and red would come back to yellow after 60ns. The state machine is not having any external input and is a free running machine synchronized by a 10ns clock (total time period = 10ns). Traffic light has an external reset control

Cross compile program which uses pthreads for bare metal

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问题 OK, this might be a very general question but I'm not to familiar with the topic and happy for any hint. I have a Cross Compiling tool chain from SoucereyCodeBench for ARM ( arm-xilinx-linux-gnueabi-). I cross compiled a library which uses the compiler Options: -DSC_INCLUDE_FX -DSC_USE_PTHREADS -pthreads -fPIC -DPIC So if I want to use the libary for bare metal program I would need pthreads for the bare metal compiler (arm-xilinx-eabi-) I guess? Otherwise my program probally wouldn't run or