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Vivado Sim Error: “root scope declaration is not allowed in verilog 95/2K mode”

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问题 When I go to simulate my top-level module in Xilinx Vivado 2016.4, I receive the peculiar error: ERROR: [VRFC 10-1342] root scope declaration is not allowed in verilog 95/2K mode [<...>/header.vh] I am using the built-in Vivado Simulator with Verilog 2001 specified. My header.vh looks like the following: `ifndef _header_vh_ `define _header_vh_ function integer clog2; input integer value; begin value = value - 1; for (clog2 = 0; value > 0; clog2 = clog2 + 1) value = value >> 1; end endfunction

Vivado Sim Error: “root scope declaration is not allowed in verilog 95/2K mode”

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Using C programming to call VHDL implementation

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问题 I'm thinking about writing a C function which basically passes an array/vector of real numbers to a VHDL implementation as an argument and the VHDL code does some computation using the array in a FPGA and returns the result back to the C function. So, my question - How do I go about writing a C function to call the VHDL implementation? Can anyone guide me in the right direction like a tutorial,API or anything? Any help will be appreciated. Thanks! :) 回答1: VHDL does not result in a run time

Moving data between processes in Spartan 3

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问题 I have two processes A and B, each with its own clock input. The clock frequencies are a little different, and therefore not synchronized. Process A samples data from an IC, this data needs to be passed to process B, which then needs to write this data to another IC. My current solution is using some simple handshake signals between process A and B. The memory has been declared as distributed RAM (128Bytes as an array of std_logic_vector(7 downto 0)) inside process A (not block memory). I'm

基于FPGA的图像处理（一）--System Generator介绍

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计算机视觉系统通常需要进行大量的信息处理才能够得到所需要的信息。目前主要有CPU、GPU、ASIC、DSP、FPGA等计算平台。常用的计算机视觉系统通过通用计算机进行视觉信息处理，但是，由于CPU的计算能力有限，对于一些计算复杂度很高的视觉算法，其处理速度常常难以满足系统的实时性需要。 GPU具有高度的并行计算能力，可以较好地解决计算速度的问题，然而，基于GPU的计算机视觉系统存在着功耗较高、体积较大的缺点，难以满足依靠自身所带电池供电并长时间工作的服务机器人等应用系统的需要。利用专用集成电路ASIC实现视觉处理算法，可以解决视觉系统性能和体积、功耗之间的矛盾，是高性能嵌入式视觉系统的一种有效的解决方案。然而，ASIC开发周期长、修改不方便，通用性较差。 FPGA可以通过编程方便地修改其内部的逻辑功能，从而实现高速的硬件计算和并行运算，是高性能嵌入式视觉系统的一种更加方便的解决方案。基于FPGA的嵌入式视觉系统的功耗远远低于基于CPU和GPU的视觉系统，FPGA的功耗通常不到1W，而高性能CPU和GPU的功耗通常都在100W以上。随着技术的不断进步，FPGA的集成度越来越高，可以实现的设计规模越来越大，而功耗则越来越低。因此，基于FPGA的嵌入式视觉系统将是计算机视觉系统的重要发展方向。使用FPGA进行图像处理时，既要对赢家有很深的了解，同时又需要对图像处理的算法很熟悉

How to instanciate Xilinx differential clock buffer with chisel3 blackboxes?

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问题 I want to write a simple chisel3 blinking led design on my AC701 kit (artix7). But to do that I have to instantiate a clock input differential buffer. Xilinx give the following verilog template to do that : IBUFDS #( .DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT") ) IBUFDS1_inst ( .O(clock1), // Clock buffer .I(clock1_p), // Diff_p clock .IB(clock1_n) // Diff_n clock ); I read on chisel documentation that I have to use «blackbox» class to instantiate it. But I can't do it. I tried this : class

How to deduce from synthesis report

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问题 I had coded the 80c51 architecture in VHDL using xilinx. In an attempt to increase the clock frequency, I had pipelined all the 80c51 instructions. The instructions were able to execute as desired, for eg. when the 1st instruction is being processed, the second instruction gets fetched. However, I only get a slightly higher clock frequency of (around +/-10Hz) despite creating a pipeline depth of 3, from the synthesis report. I figured out that the bottleneck is due to one operation as

Verilog, FPGA, use of an unitialized register

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问题 I have a question about what seems to me odd behavior of an AGC/SPI controller I'm working on. It's done in Verilog, targeting a Xilinx Spartan 3e FPGA. The controller is a FSM that relies on external inputs to start. The state of the FSM is stored in state_reg which is not explicitly initialized, as I thought an uninitialized register would default to zero. When I implemented the controller the FSM would not run. Monitoring the SPI bus I observed no activity. To monitor the FSM i routed the

How to check time performances in a C++ program on Zedboard

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问题 I have implemented a C++ code on a Zedboard. It compiles and runs perfectly, but now i would like to check the performances in order to optimize some functions. I have checked some threads here (Testing the performance of a C++ app) and here (Timer function to provide time in nano seconds using C++), but i don't really understand how to apply it mon code ... To make things clear : I'm not good at C++, I have never really learned the language formally but only used it several times with

vivado中license获取及安装方法

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vivado中license获取及安装方法（1）先说下license安装方法（具体获取见后文）这里以win7系统为例说明，开始–》所有程序–》找到xilinx安装文件Manage xilinx license如下图所示：双击打开如下所示，依次点击Load license->Copy license 在弹出的对话框中选择对应的license文件即可（2）关于license的获取见下链接链接：https://pan.baidu.com/s/1AKAaNEggSWuRhOQSKJWc8Q 提取码：v1yz 来源： CSDN 作者： 541板哥链接： https://blog.csdn.net/u011816009/article/details/103569000