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Registering Platform Device with info from Device Tree

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问题 I am using Petalinux for a Xilinx Zynq application, and I am new to kernel driver development. I created a kernel module for a platform driver for an AXI FIFO interface. The devices seems to be recognised from the device tree using the .of_match_table, since I can see the correct memory space reserved with cat /proc/iomem . If I search for the driver name xxx I get ./lib/modules/4.4.0-xilinx/extra/xxx.ko ./sys/bus/platform/drivers/xxx ./sys/module/xxx ./sys/module/xxx/drivers/platform:xxx I

Too many comps of type “BUFGMUX” found to fit this device. (Ethernet Design)

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问题 I'm designing an Ethernet MAC Controller for Spartan 3E FPGA. IOBs have reached 109%. I still proceeded with the generation of bitstream. I then encountered this error: Too many comps of type "BUFGMUX" found to fit this device. What does this mean? (I'm pretty sure that running the Spartan 3e can run the Ethernet since there is already an IP of Ethernet lite MAC for Spartan 3e. Also, it has more pins than I have in my module. Why does it have then 109% of IOBs?) I also tried commenting the

Why dynamic power consumption is always zero?

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问题 I want to get an accurate power report that contains real dynamic and static power consumption. I'm working on Xilinx spartan3 board. My code has no errors but after selecting the "Generate Text Power Report" in ISE (Xilinx synthesis tool), always the power report shows that my design has no dynamic power consumption. (Why?) Power report : Dynamic = 0.00 Quiescent = 59.84 Total = 59.84 My code : LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY SRAM IS PORT( clk : IN std_logic; wr : IN std

Non-static loop limit exceeded

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问题 I want to implement the K&R algorithm for hamming weight calculation of 256 bit vector. I have written my code in vhdl as: entity counter_loop is Port ( dataIn : in STD_LOGIC_VECTOR (255 downto 0); dataOut : out STD_LOGIC_VECTOR (8 downto 0); threshold : in STD_LOGIC_VECTOR (8 downto 0); clk : in STD_LOGIC; flag : out STD_LOGIC); end counter_loop; architecture Behavioral of counter_loop is signal val : STD_LOGIC_VECTOR (255 downto 0) := X

二、zedboard 交叉工具链安装

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【推荐】2019 Java 开发者跳槽指南.pdf(吐血整理) >>> zynq大部分参考资料参考( http://www.wiki.xilinx.com/ )和官方手册第一步：首先需要建立xilinx的交叉编译环境；下载( https://pan.baidu.com/s/1midNxaS )解压搜索arm-2010.09-62-arm-xilinxa9-linux-gnueabi.bin放在/home目录下第二步：ctrl+alt+t然后打开命令窗口执行sudo dpkg-reconfigure dash选择NO 第三步：执行sudo ./xilinx-2011.09-50-arm-xilinx-linux-gnueabi.bin 一路YES直到操作完成第四步：执行sudo gedit ~/.bashrc 打开环境变量第五步：在文件尾填入 export CROSS_COMPILE=arm-xilinx-linux-gnueabi- export PATH=/root/CodeSourcery/Sourcery_CodeBench_Lite_for_Xilinx_GNU_Linux/bin/:$PATH 保存并且退出第六步：执行su 进入超级权限执行arm-xi 按TAB键看是否补全命令补全即完成zynq的交叉编译工具链安装来源： oschina 链接：

三、zedboard Linux内核编译

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【推荐】2019 Java 开发者跳槽指南.pdf(吐血整理) >>> 我们的目标是生成zedboard的启动文件首先需要工具和输入文件： Tools Required Xilinx SDK Input Files Required FSBL u-boot uImage uRamDisk.image.gz devicetree.dtb Output Files Produced boot.bin 首先需要安装一些必要的软件包 sudo apt-get install device-tree-compiler openssl-devel libncurses5-dev libncursesw5-dev u-boot-tools 一、uboot编译第一步：下载uboot源代码，( https://github.com/Xilinx/u-boot-xlnx/releases/tag/xilinx-v2016.3 ) 我已经上传百度云盘( https://pan.baidu.com/s/1dE4jOm1 ) 第二步：su 进入超级权限 sudo tar -zxvf xilinx-v2016.3.tar.gz cd u-boot-xlnx-xilinx-v2016.3/tools/ export PATH= pwd :$PATH 第三步：返回u-boot-xlnx-xilinx-v2016

How to fix Xilinx ISE warning about sensitivity list?

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问题 I synthesized my design with Xilinx ISE 13.1. Target device is Virtex 5. Then I encountered this warning: WARNING:Xst:819 - "F:/FRONT-END/h264/inter/src/eei/eei_mvd.vhd" line 539: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <mvd_l0<3

Verilog Placement Constraints with Generate Statements

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问题 I'm trying to generate an array of latches that are placed adjacent to each other using a Generate statement. I've been trying to use the Xilinx constraint "RLOC" to do this, but I haven't been successful. The code below won't successfully implement, but should illustrate what I'm trying to obtain. The issue with the code below is that "i" in the constraint call isn't being converted into a string, which is what the call is looking for. Does anyone have experience doing this? I'm using a

GHDL simulator doesn't support vhdl attributes without error?

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问题 I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; entity vivado_rtl_island is port( -- Clocks i_m50_clk :in std_logic; i_m50_rst :in std_logic; -- APB Command Inteface s_paddr :in std_logic_vector(31 downto 0); s_psel :in std_logic; s_penable :in std_logic; s_pwrite :in std_logic; s_pwdata :in std_logic_vector(31 downto 0); s_pready :out std_logic; s_prdata

Why I can not input value to inout type?

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问题 I create this code from this curcuit Image Here And this is Error image Image Here This curcuit is Quadruple Bus Transcievers with 3-state outputs Verilog Code module Q52QuadrupleBus3Stlate(GAB,GBA,A,B); inout [3:0] A,B; input GAB,GBA; reg winA,winB; assign B = (GAB==1&&GBA==0) ? winA : 4'hz; assign A = (GAB==0&&GBA==1) ? winB : 4'hz; always @ (GAB or GBA) begin winA <= A; winB <= B; end endmodule Test Bench `timescale 1ps / 1ps module Q52TestBench; reg GAB; reg GBA; // Bidirs wire [3:0] A;