Why does the following redeclaration error happen in verilog?

问题

I'm trying to implement a simple verilog code as below:

module test1(
    input ACLK,
     input RST,
    output test_output1,
    output test_output2
    );

//wire ACLK;
//wire RST;
reg test_output1;
reg test_output2;


assign test_output1 = ACLK;

always @(posedge ACLK or negedge RST)
begin
    if(!RST) 
    begin
        //test_output1 <=0;
        test_output2 <=0;
    end 
    else 
    begin
        //test_output1 <=0;
        test_output2 <=1;
    end
end 


endmodule

I get the following error message when I try to synthesize it in Xilinx ISE:

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "test1.v" in library work
ERROR:HDLCompilers:27 - "test1.v" line 30 Illegal redeclaration of 'test_output1'
ERROR:HDLCompilers:27 - "test1.v" line 31 Illegal redeclaration of 'test_output2`

I am unable to resolve this error. Any help would be highly appreciated.

回答1:

If you declare the directional of the port in the portlist, you must also declare the type. This is referred to as an ANSI style header.

There is also a non-ANSI style header that separates the portlist, directional, and type. If you are fallowing IEEE1364-1995 convention then you must use non-ANSI style and you cannot declare the type (e.g. output reg test_output2; is illegal, while output test_output2; reg test_output2; is legal). Since IEEE1364-2001 ANSI and non-ANSI style is supported (and the non-ANSI allows output reg test_output2;). All modern Verilog simulators are SystemVerilog (IEEE1800) simulators, therefore it is the designers choice. (ANSI style is more popular as it is less typing).

ANSI style header:

module test1(
  input ACLK,
  input RST,
  output test_output1,
  output reg test_output2 );

Non-ANSI style header:

module test1( ACLK, RST, test_output1, test_output2 );
  input ACLK;
  input RST;
  output test_output1;
  output test_output2;

  reg test_output2;

Note: With IEEE1364, you can not drive a reg with an assign statement, it must be a net type. IEEE1800 has softened the rule the it is recommenced logic in stead of reg, but generally if you are going to use assign then you should be assigning a net (e.g. wire).

回答2:

Add following modification:

You used test_output1 in assign statement so it should be of type wire.

module test1(
  input wire ACLK,
  input wire RST,
  output wire test_output1, 
  output reg test_output2  
);

You have already declared test_output1 and test_outpu2 as output and it is by default of type wire, so you just have to implicitly specify wire or reg according to usage,
```
// reg test_output1;
// reg test_output2;
```

来源：https://stackoverflow.com/questions/37200244/why-does-the-following-redeclaration-error-happen-in-verilog

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verilog

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