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Signal is connected to following multiple drivers

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问题 I trying to run the following and I receive this error: Here's the Verilog code: module needle( input referrence,input penalty,output index[7:0]); //inout input_itemsets; //input referrence; //input penalty; //output index; parameter max_cols=8; // wire index[7:0]; wire referrence; wire penalty; //wire input_itemsets; genvar i,idx; generate for( i = max_cols-4 ; i >= 0 ; i=i-1) for( idx = 0 ; idx <= i ; idx=idx+1) begin assign index[i] = (idx + 1) * max_cols + (i + 1 - idx); //assign index =

VHDL - “Input is never used warning”

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问题 I've written a program in VHDL (for Xilinx Spartan-6) that increments a counter whilst a button is pressed and resets it to zero when another button is pressed. However, my process throws the error WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected... for the reset variables - despite the fact that it is used both in the sensitivity of the process and as a condition (just as much as button , yet that doesn't get flagged!). binary_proc : process(CLK_1Hz,

HOW do I write from a Spartan6 to the Micron external Cellular RAM on the Nexys3 FPGA Board?

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问题 I have looked everywhere, the datasheet, the Xilinx website, digilent, etc. etc. and can't find anything! I was able to use the Adept tool to verify that my Cellular RAM is functioning correctly, but I just can't find any stock VHDL code as a controller to write data to and read data from it!! Help!! 回答1: Found this link but it's for asynchronous mode, which is not nearly fast enough: http://embsi.blogspot.com/2013/01/how-to-use-cellular-ram-from-micron.html Eventually found this on the Nexys

BRAM_INIT in VHDL

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问题 I am simulating a processor based design where the program memory contents are held in a BRAM. I am realizing the program memory using VHDL (inferring BRAMs). I am trying to avoid CoreGen because I want to keep the design portable. Eventually this design will go to an FPGA. I am looking to see if there is a way to initialize memory contents of the BRAMs using VHDL generics ? I understand that Coregen uses COE file to initialize the BRAM but do we have a VHDL code based way to do this ? Let me

xilinx官网下载vivado速度慢的解决方法（适用于所有版本）

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1.进入xilinx官网，选择需要下载的vivado版本，我选择下载Vivado HLx 2017.4: All OS installer Single-File Download (TAR/GZIP - 16.17 GB) 2.从浏览器中下载，速度还不到30kb/s，简直就是龟速 3.为了提高下载速度，选择从迅雷中下载，从浏览器下载界面复制下载地址 https://xilinx-ax-dl.entitlenow.com/dl/ul/2017/12/17/R209897626/Xilinx_Vivado_SDK_2017.4_1216_1.tar.gz/51370b1ad9c46e6f436cf45cd4b0b92b/5DEF561A?akdm=0&filename=Xilinx_Vivado_SDK_2017.4_1216_1.tar.gz 4.打开迅雷，点击添加，下载速度得到大幅提升 5.完事，等待下载完成来源： CSDN 作者：不吃老鼠的猫159 链接： https://blog.csdn.net/qq_39509561/article/details/103471606

Getting the IEEE Single-precision bits for a float

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问题 I need to write an IEEE single-precision floating point number to a 32-bit hardware register at a particular address. To do that, I need to convert a variable of type float to an unsigned integer. I can get the integer representation like this: float a = 2.39; unsigned int *target; printf("a = %f\n",a); target = &a; printf("target = %08X\n",*target); which returns: a = 2.390000 target = 4018F5C3 All good. However this causes a compiler warning "cast.c:12: warning: assignment from incompatible

Generate State Machine graph from VHDL code?

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Is there any quite good tool to generate State Machine graph from VHDL code? I'm using Xilinx ISE Webpack. Cheers! Active HDL has a feature called " Code2Graphics " which supports this. Additionally, some synthesis tools (typically ones you would have to pay for) also support this. Note that an RTL view is more commonly available in synthesis tools (such as XST). Modelsim SE (and DE?) have these kind of things. But, not for free :-( 来源： https://stackoverflow.com/questions/6240016/generate-state-machine-graph-from-vhdl-code

mmap EINVAL error on UIO device

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I have trouble mapping physical memory on Xilinx Zynq after attempting to use UIO instead of mapping directly /dev/mem . While the plan is to run the application as a normal user instead of root this is still being run as root . Apparently the first mapping is successful while the rest done to the same file descriptor 12 ( /dev/uio/ps2pl ) fail. While the obvious difference is the offset, it is within the range (see device tree) and it is properly page aligned. This application was working well with /dev/mem . The error observed by running with strace is: open("/dev/uio/ps2pl", O_RDWR|O_SYNC)

xilinx基础入门

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2019.09.03 一、基础部分及语法一、FPGA程序的固化 [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information. 1、在C语言代码中，行结尾反斜杠\ 起到换行作用，用于宏定义和字符串换行。其中宏定义使用居多。如果一行中有很多元素导致太长影响阅读，可以在结尾加 \ 的方式实现换行，编译时会忽略\以及其后的换行符，当做一行处理。………\就是表示一行不间断。 2、关于各种电压： VCCINT：内部PL核心电压 VCCAUX：辅助PL电压 VCCBRAM：PL BRAM电压 VCCPINT:PS内部核心电压 VCCPAUX：PS辅助电压 VCCDDR:DDR RAM的工作电压 VREFP：XADC正参考电压 VREFN：XADC负参考电压 3、 #ifdef __cplusplus Extern “C”{ #endif 代码说明：为了在C++代码中调用用c写成的库文件，就需要用extern”C”来告诉编译器：这是一个用C写成的库文件，请用C的方式来链接它们。二、断言函数 #define Xil_AssertNonvoid(Expression) \ { \ if (Expression) { \ Xil

How to instanciate Xilinx differential clock buffer with chisel3 blackboxes?

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I want to write a simple chisel3 blinking led design on my AC701 kit (artix7). But to do that I have to instantiate a clock input differential buffer. Xilinx give the following verilog template to do that : IBUFDS #( .DIFF_TERM("TRUE"), .IOSTANDARD("DEFAULT") ) IBUFDS1_inst ( .O(clock1), // Clock buffer .I(clock1_p), // Diff_p clock .IB(clock1_n) // Diff_n clock ); I read on chisel documentation that I have to use «blackbox» class to instantiate it. But I can't do it. I tried this : class IbufdsParam extends VerilogParameters { val DIFF_TERM = "TRUE" val IOSTANDARD = "DEFAULT" } class IBUFDS