vivado

问题 I'm trying to build the https://github.com/olajep/parallella-fpga/tree/2016.11 project. after I cloned it, I've tried to run "make" command in the parallella-fpga folder but I get this message in the terminal: make -C AdiHDLLib/ lib make[1]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib' make -C library/ all make[2]: Entering directory '/home/hadi/Vivado/project/parallella-fpga/AdiHDLLib/library' make -C axi_clkgen make[3]: Entering directory '/home/hadi/Vivado

问题 What did I do wrong with the selected signal assignment in my VHDL code? with s select x <= a when (s = '1') else y <= a when (s = '0'); I also tried this: with s select x <= a when '1'; with s select y <= a when '0'; 回答1: It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0' The use of select should be done in cases when you want to create

问题 I wrote some cross platform VHDL libraries for Xilinx XST, iSim, Altera Quartus II, Mentor Graphics QuestaSim and GHDL. Now I wanted to port my ISE 14.7 project, which uses these libraries to Vivado 2014.4, but one library seems to have fatal problems. My library physical defines several new user defined physical types like: FREQUENCY and BAUD ; conversion functions and report functions. One main use case is the calculation of delay or counter cycles for a given delay and system frequency. So

问题 I have never come across this problem before when uses black-boxes inside custom IP. Usually I instantiate and add the custom IP to the project, and then instantiate and add the black box IP modules (the black boxes are inside the custom IP) to the project. For some reason now I am getting the classic [Project 1-486] Could not resolve non-primitive black box cell 'FX_Thomas_Core_0FX_Thomas_Core_0FX_Thomas_Core_0Thomas_Sub' instantiated as 'Subtractor' ["c:/Users/Sam/Documents/Zynq7020/FX

问题 I am trying out programming my digilent FPGA through the vivado command line. After opening the hardware server I can program my device as follows... program_hw_devices [get_hw_devices xc7a100t_0] Then if I run puts [get_hw_devices xc7a100t_0] it outputs xc7a100t_0 which leads me to think that I should be able to just do something like program_hw_devices xc7a100t_0 . This however fails and I get the following output. ERROR: [Common 17-161] Invalid option value 'xc7a100t_0' specified for 'hw

问题 I am getting through the tutorial of Nexys 4 DDR and I am implementing a simple MUX library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VComponents.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity lab1_2_1 is Port ( SW0 : in

问题 I am running Vivado HLS 2014.4 (x64) on Ubuntu 14.04 x64. Everything works in Vivado HLS 2012. In Vivado HLS 2014.4 GUI and Synthesis works but compilation of testbench does not. I am getting thousands of errors like this: Building file: /home/nic30/vivado/tb_axis_test.cpp Invoking: GCC C++ Compiler g++ -DAESL_TB -D__llvm__ -D__kernel -D__global -Dglobal -Dlocal -D__local -Dconstant -D__constant -Dprivate -D__private -D__private -I/opt/Xilinx/Vivado_HLS/2014.4/include/ap_sysc -I/opt/Xilinx

问题 Just wanted to ask, what is the difference between secure and non-secure transactions when it comes to AXI bus transactions? What are the performance implications of either transaction? 回答1: Trusted transactions are a part of ARM's TrustZone policy. It requires an additional pin to indicate a secure connection. It only allows communication with the secure section of the processor. It is a software solution to restrict access to hardware in the case of root access on the OS. It acts as a

问题 I'm trying to clone and make this project to use in Vivado: https://github.com/olajep/parallella-fpga/tree/2016.11 after I've cloned it then I use git submodule init and the gir submodule update command. after that I used make command and I get this message: Traceback (most recent call last): File "/usr/lib/command-not-found", line 28, in <module> from CommandNotFound import CommandNotFound File "/usr/lib/python3/dist-packages/CommandNotFound/CommandNotFound.py", line 19, in <module> from