问题
What did I do wrong with the selected signal assignment in my VHDL code?
with s select x <= a when (s = '1')
else y <= a when (s = '0');
I also tried this:
with s select x <= a when '1';
with s select y <= a when '0';
回答1:
It's not completly clear what you want to do. From what you showed us, it seems to me that you want to create a demux controlled by signal s (1 input, 2 outputs), where x <= a when s='1' and y <= a when s='0'
The use of select should be done in cases when you want to create a mux (n inputs, 1 output). That is, the opposite of a demux!
I would recommend you to use a simple if statement to create a demux.
Example:
if s='1' then x <= a; else y <= a; end if;
来源：https://stackoverflow.com/questions/53415482/why-does-my-selected-signal-assignment-not-work