computer-architecture

问题 I have encountered the following question and can't be sure on the answer. Do you have any suggestions, any help would be much appreciated. The Fibonacci sequence F(n) is defined by F(1)=1, F(2)=1, and Fn=F(n-2) + F(n-1) for all integers n>= 3. What is the minimal number of D flip-flops required (along with combinational logic) to design a counter circuit that outputs the first seven Fibonacci numbers (i.e., F1 through F7 ) and then wraps around? (A) 3 (B) 4 (C) 5 (D) 6 (E) 7 Thanks in

问题 What can I extract from computer to identify it. MAC address, Hard disk serial number, then? 回答1: I don't have a code to show you right now but i have done similar things, by cominning CPU Id and Harddrive serial No, that's how you get the unique no; try this; http://www.vcskicks.com/hardware_id.php 来源： https://stackoverflow.com/questions/15546151/how-to-retrieve-unique-identification-from-computer

问题 My PC has a GTX 580 (compute capability 2.0). I want to compile a CUDA source that uses dynamic parallelism, a feature introduced in compute capability 3.5. I know I will not be able to run the program on my GPU, however, it should be possible to compile this code on my machine. I'm assuming this because I can compile with no problems the CUDA samples that use 3.5 capability. These samples come with Visual Studio projects that were "manually generated" (I guess). I believe my problem is with

问题 I only learned the equation all access = instruction access + data access read = instruction access + load write = instruction access + store I think that I'm not fully understand the difference between 'instruction access' and 'data access' The most curious thing is that why 'read' include 'instrution access'. Could anybody explain this??? :'-( 回答1: The processor must know what to do before doing it. So, instruction access is like knowing what operation to do and knowing the source and

问题 My questions are related to memory? What is the difference between alignment and addressable? If a memory is byte addressable and word aligned then can't we directly have a word addressable memory? Also when we say we have a block transfer what does it mean. As in if the size of the block is greater than word (databus),then does that mean it takes more than one cycle to transfer. 回答1: Short answer Addressability refers to the smallest unit of memory that can be accessed, while alignment

问题 the question is as follows : Write down all the real numbers that have more than 1 representation in IEEE-754 of single precision. Now, considering +0 and -0 are different, are there any numbers that have this property? 回答1: There are none. The IEEE754 representation is canonical , which means that all numbers have precisely one representation if any, and no others. Format of an IEEE754 single-precision floating-point number 31 0 seeeeeeeemmmmmmmmmmmmmmmmmmmmmmm Mapping to (-1)^s * 2^

问题 What should be a good approach to simulate MIPS pipe lining ? Like should pipeline simulates in forward direction or in backward direction ? I am confused. I have instruction set and i have disassembled the instructions but i need some direction to move further. 回答1: The advantage of simulating the pipeline stages "backwards" (e.g. in reverse order like writeback, cache, alu, register, decode, fetch) is that each stage can read the variables that represent the input latches and then simply

问题 Specifically this question is about flat and segmented model in real mode. I am reading a book on assembly which mentions that on DOS the COM files use flat memory model and EXE files use segmented memory model. However I am not understanding what tells DOS which memory model to use. I am asking this question because I am reading about bootloaders. 回答1: COM files used a "flat memory model" in the sense that the segment registers were alll set by DOS when the program was loaded to point to the

问题 I ran perf analysis on the following empty program, #include <stdio.h> int main() { } After compiling and running perf stat ./a.out I got the following output saying (along with other data like number of cycles, task-clock etc): 418,869 instructions # 0.87 insns per cycle The number of instructions changes during every 'perf' analysis on the same elf. My actual need is to find the number of instructions in a particular function I wrote. So I will be subtracting the above number from the

问题 Registers are the fastest memories in a computer. So if we want to build a computer with just registers and not even caches is it possible? I think of even replacing the magnetic discs with registers although they are naturally volatile memories. Do we have some nonvolatile registers for that use? It would become so fast! I'm just wondering if that could be happen or not? 回答1: The very short answer is yes, you could in theory, but it doesn't really work in real life . Let me explain... The