computer-architecture

问题 This is a question based on Direct Mapped Cache so I am assuming that it's ok to ask here as well. Here is the problem I am working on: The Problem: " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 64 byte lines, how many bits are in each of the following address fields for the cache? 1) byte 2) Index 3) Tag?" First I defined the terms in this problem and used the other Stack Overflow Direct

问题 Cache is controlled by cache hardware transparently to processor, so if we use volatile variables in C program, how is it guaranteed that my program reads data each time from the actual memory address specified but not cache. My understanding is that, Volatile keyword tells compiler that the variable references shouldn't be optimized and should be read as programmed in the code. Cache is controlled by cache hardware transparently, hence when processor issues an address, it doesn't know

问题 As the comp.lang.c FAQ says, there are architectures where the null pointer is not all bits zero. So the question is what actually checks the following construction: void* p = get_some_pointer(); if (!p) return; Am I comparing p with machine dependent null pointer or I'm comparing p with arithmetic zero? Should I write void* p = get_some_pointer(); if (NULL == p) return; instead to be ready for such architectures or is it just my paranoia? 回答1: According to the C spec: An integer constant

问题 I am taking a course on Computer Architecture. I found this website from another University which has notes and videos which are helping me thus far: CS6810, Univ of Utah. I am working through these series of notes but am in need of some explanation on some of the example problems. I am currently looking at Problem 7, on page 17-18. The solutions are given in the notes on page 18 but I am somewhat unsure of how the professor is reaching the conclusions. He states on his class webpage that he

问题 I am trying to find a simple, easy to understand explanation of instruction set and instruction set architecture (if there is a difference.) I can only find technical references. I would appreciate if somebody can help explain in a few paragraphs what it is and its importance to a programmer. 回答1: Instruction Set would be the repertoire of a particular language. Instruction Set Architecture (ISA) is the way that repertoire is understood. Let's think of the differences between human and

问题 The values of a,x,y if 47x80 is the 10's complement of yaya0 is: I calculated the 10's complement of yaya0 to be 100,000-yaya0 and then. 47x80=100,000-yaya0 Now how to find values ? 回答1: 47080 + 100x = 100000 - (10000y + 1000a + 100y + 10a) 52920 = 100x + 10100y + 1010a ==> a = 2 otherwise you won`t get the 2 as tens 50900 = 100x + 10100y this can be split up in 5 = y and 9 = x + y so a = 2 x = 4 y = 5 回答2: 47x80 represents a number where 'x' is the hundreds. So does yaya0 where 'y' represent

问题 I am doing a practice exam question. The Question is Is there anything wrong in this line of LC3 code? (The starred line) ADD R3, R3, 0; **BRNZ ISPOS;** HALT .BLKW 250 ISPOS NOT R3, R3 .... I saw that the starred line is Branch and the condition codes are negative and zero, basically go to label ISPOS if the condition code is negative or zero or halt the program otherwise. I would say that this line of LC3 code has nothing wrong with it. Does anyone see any problems with it? 回答1: Yes, there

问题 I'm finishing up a project and a requirement is two-way handshaking between functional units inside our processor. I know what it is but is there any 'standard' or a good simple example of it? Only thing I can think of between two units, when there's a data-line between them and when X sends to Y, a separate 'sent' signal is given. When Y receives a 'received' signal is sent to X on another wire. Once X reads that received signal it stops sending data on the data-line and sets sent wire to 0

问题 This question already has answers here : Closed 8 years ago . Possible Duplicate: Determine word size of my processor It is One Interview question today. But I didn't know ... I think the interviewer meaned the word size of cpu. I find an answer like this: int cpu_bits(void *dummy1, void *dummy2) { long offset = (long)&dummy2 - (long)&dummy1; int ret = 0; if (8 == offset) ret = 64; else if (4 == offset) ret = 32; else if (2 == offset) ret = 16; else if (1 == offset) ret = 8; else ret = -1;

问题 Here is the problem I am working on The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address space of the workstation? I defined the different terms in the problem Word Size - Processor natural unit of data. The word size determines the amount of information that can be processed in one go Byte Level Addressing - Hardware architectures that support accessing individual bytes within a word 64