computer-architecture | 易学教程

Are Golang binaries portable?

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问题 Suppose I'm a primarily Linux user, but I'm developing an application in Go that I want to be cross platform. I've searched around, but I can't seem to find information to absolve the following: If I go install a binary on my amd64 Ubuntu system, will it also work on anyone else's 64-bit Ubuntu/Debian system? How can I use go install to build an x86_64 binary that will also run out-of-the-box on 32-bit Debianlikes? If I must use Windows to make a binary which will run on Windows, how can I

Deploying to OS X 10.6 and “-fobj-arc is not supported on platforms using the legacy runtime”

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问题 Background: I'm building an app for OS X with deployment target of 10.6. I have not converted my app to ARC completely, but I am adding a few new classes which would benefit from ARC, so I have set the -fobj-arc compiler flag for those classes. Compiling fails for Universal 32/64-bit Intel architecture, with error -fobj-arc is not supported on platforms using the legacy runtime . Building for 64-bit only succeeds. I'm not well versed in low level architecture. My question is: what is the

cache reads and writes

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问题 I'm reading about cache write policies, and I just want to know if I'm understanding this correctly. When a read results in a cache miss, it'll get that block of memory and put it in the cache. A cache write miss then would mean that the location in memory that the program wants to write into is not within the cache, correct? So I'm reading the description of write-back , which is as follows according to wikipedia: initially, writing is done only to the cache. The write to the backing store

32-bit App with dynamic library crash on 64-bit device

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问题 I am facing the following scenario: 32 bit device + app armv7 + dynamic library armv7 arm64 = work 64 bit device + app armv7 + dynamic library armv7 arm64 = doesn't work doesn't work - app crashes on load with the following error: dyld error message library not loaded reason no suitable image found Any explanations? 回答1: Explanation : 32 bit binaries loaded on 64 bit devices fail to do so since the 32 bit pagesize has been changed from 4096 bytes to 16384 bytes in iOS 9. Conclusion : 32-bit

Can branch prediction crash my program?

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问题 Going trough chapter 3 of this book called Computer Systems Architecture: A programmer's perspective, it is stated that an implementation like testl %eax, %eax cmovne (%eax), %edx is invalid because if the prediction fails, then we'll have NULL dereferencing. It is also stated that we should use branching code. Still, wouldn't using conditional jumps lead to the same result? For example: .L1: jmp *%eax testl %eax, %eax jne .L1 Is it possible to trick gcc to output something like that for an

Word Sizes and It's Indications

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Please see below a question regarding word sizes in various instruction set architectures, and how that ties to assembly languages. Thank you for any and all help. First a few facts (please correct me if any of these are wrong). The word size of a processor architecture indicates (EDIT: Some of these were wrong, please see Seva's post below) : The largest size of each register The largest size of each memory address (amount of memory that can be addressed) The largest integer the CPU can process in a single instruction Largest piece of data that can be transferred to and from the working

Writing a Register File in VHDL

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问题 I am trying to write a register file in VHDL. The file contains 16 64-bit registers. Each cycle, two registers are read and one register is written (given that writing is enabled). There should be a data bypass (forwarding) so that the value just written is forwarded directly to the output if we are reading and writing to/from the same register in a single cycle. My idea was to write on the rising edge and read on the falling edge of the clock in order to complete this in one cycle. However,

Why doesn't this code scale linearly?

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问题 I wrote this SOR solver code. Don't bother too much what this algorithm does, it is not the concern here. But just for the sake of completeness: it may solve a linear system of equations, depending on how well conditioned the system is. I run it with an ill conditioned 2097152 rows sparce matrix (that never converges), with at most 7 non-zero columns per row. Translating: the outer do-while loop will perform 10000 iterations (the value I pass as max_iters ), the middle for will perform

Why do we need different CPU architecture for server & mini/mainframe & mixed-core? [closed]

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问题 As it currently stands, this question is not a good fit for our Q&A format. We expect answers to be supported by facts, references, or expertise, but this question will likely solicit debate, arguments, polling, or extended discussion. If you feel that this question can be improved and possibly reopened, visit the help center for guidance. Closed 7 years ago . I was just wondering what other CPU architectures are available other than INTEL & AMD. So, found List of CPU architectures on

Cache eviction from L1 cache on L2 eviction

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问题 I have a basic question about the policy followed by the memory system. Consider a core with private L1 and L2 caches. After L2 cache we have a bus on which the coherence traffic runs. Now, if a cache line for address(X) is evicted from the L2 cache, is it necessary to evict that address from the L1 cache ?? The reason for eviction can be that it helps in maintaining the invariant of the coherence protocol [if a line in l2 shows invalid this core does not contain this address]. 回答1: There are