In this x86-64 instruction encoding documentation, what's the use of having 8, 16, 32, 64 bit GPRs? [duplicate]

放肆的年华 提交于 2021-01-28 07:37:10

问题


I'm learning (slowly and painfully) about x86-64 instructions, and found this chart in the documentation I'm reading:

I think "GP" in this context refers to the GPR (General Purpose Registers) I "understand" the register structure for x86-64 is like so:

And so my first comprehension of this was that a 64 bit system has 64 bits of cache allocated to the GPR in a CPU and can handle larger register values, and the 32 bit registers act as a fall-back for compatibility with processors that only allocate 32 bits to the GPRs, and so on and so forth down to a theoretical 8 bit processor (or perhaps one exists).

But I was also wondering if it's alternatively a way of writing fewer bits to the registers when more precision isn't needed, and therefore operate more efficiently or faster.

But looking at that top table, it seems like since the xReg column assigns a single binary value to each category of GPR segment (0000=> AL, AX, EAX, RAX, ...) makes it seem like there's a specific mode of operation decided ahead of time and the developer doesn't work with all the different register sizes. or maybe there's other bits in the instruction that define which mode is being used?

What's the purpose of the multiple register sizes? Is it compatibility with various CPU GPR sizes where a 64 bit CPU only uses 64 bit registers? or is it about writing smaller register values for efficiency?

来源:https://stackoverflow.com/questions/64482535/in-this-x86-64-instruction-encoding-documentation-whats-the-use-of-having-8-1

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