问题
In ARM architecture, if an ARM to Thumb mode switch occurs, will a pipeline stall occur? If so, how many cycles are affected? Is this same for Thumb to ARM mode switching ? Does this behavior vary with different ARM processors ?
回答1:
Assuming you switch in the sensible way (with BLX/BX LR), any modern core will predict that (assuming the branch predictor isn't turned off, of course). Writing to the PC directly is a little more variable - generally, big cores might predict it but little cores won't - but is generally best avoided anyway.
Otherwise an interworking branch is AFAIK no different to a regular branch, so if it isn't predicted the penalty is just a pipeline flush. The only other way to switch instruction sets is via an exception return, which is a synchronising operation for the whole core (i.e. not the place to be worrying about performance).
回答2:
No, not at all.
The cost is just like any other branch instruction. If the predictor hits, it's free, if not, it costs the usual 13 cycles.
There's no additional hidden hiccups due to the switching.
Therefore, you can use the interworking mode without worrying about potential penalties related to the mode switching.
来源：https://stackoverflow.com/questions/24780301/does-a-pipeline-stall-occur-on-an-arm-to-thumb-switch