x86-64

What is the most efficient way to load a x64 ymm register with 4 doubles evenly spaced i.e. a contiguous set of doubles 0 1 2 3 4 5 6 7 8 9 10 .. 100 And i want to load for example 0, 10, 20, 30 4 doubles at any position i.e. i want to load for example 1, 6, 22, 43 zx485 The simplest approach is VGATHERQPD which is an AVX2 instruction available on Haswell and up. VGATHERQPD ymm1, [rsi+xmm7*8], ymm2 Using dword indices specified in vm32x, gather double-pre-cision FP values from memory conditioned on mask specified by ymm2. Conditionally gathered elements are merged into ymm1. which can achieve

So I am currently learning about stack frames, and I wanted to experiment printing the stack frame (manually) of a function. I have the following picture in mind of a stack frame (I may be wrong): | | 0xffff0fdc +--------------------------------+ | ... | 0xffff0fd8 +--------------------------------+ | parameter 2 | 0xffff0fd4 +--------------------------------+ | parameter 1 | 0xffff0fd0 +--------------------------------+ | return address | 0xffff0fcc +--------------------------------+ | local variable 2 | 0xffff0fc8 +--------------------------------+ | local variable 1 | 0xffff0fc4 +----------

I'm still uncertain how registers are being used by the assembler say I have a program: int main(int rdi, int rsi, int rdx) { rdx = rdi; return 0; } Would this in assembly be translated into: movq %rdx, %rdi ret rax; I'm new to AT&T and have hard time predicting when a certain register will be used. Looking at this chart from Computer Systems - A programmer's perspective , third edition, R.E. Bryant and D. R. O'Hallaron: charter Is it certain in which register arguments and variables are stored? Only at entry and exit of a function. There is no guarantee as to what registers will be used

As we know on x86 architecture the acquire-release consistency provided automatically - i.e. all operations automatically ordered without any fences, exclude first store and next load operations. (As said Herb Sutter on page 34: https://onedrive.live.com/view.aspx?resid=4E86B0CF20EF15AD!24884&app=WordPdf&authkey=!AMtj_EflYn2507c ) If we put MFENCE(LFENCE+SFENCE) between them, then store can't be reordered, and load can't be reordered - i.e. we provided sequential consistency . But if we marked memory as WC(Write Combined) , then do we have any consistency automatically without any fences, may

Are Intel x86_64 processors not only pipelined architecture, but also superscalar? Pipelining - these two sequences execute in parallel (different stages of the same pipeline-unit in the same clock, for example ADD with 4 stages): stage1 -> stage2 -> stage3 -> stage4 -> nothing nothing -> stage1 -> stage2 -> stage3 -> stage4 Superscalar - these two sequences execute in parallel (two instructions can be launched to different pipeline-units in the same clock, for example ADD and MUL): ADD(stage1) -> ADD(stage2) -> ADD(stage3) MUL(stage1) -> MUL(stage2) -> MUL(stage3) Yes, contemporary Intel

Purpose : I was trying to take advantage of the RIP mode in x86-64. Even though the assembly performs as expected on its own, the shellcode does not. The Problem : Concisely what I tried was this, jmp l1 str1: db "some string" l1: other code lea rax, [rel str1] I used the above at various places, it failed only at certain places and succeeded in other places. I tried to play around and could not find any pattern when it fails. When variable(str1: db instruction) position is after the instruction accessing it, it never failed(in my observations). However, I want to remove nulls, hence I placed