Verilog Module Warning
问题 Im writing a multiplexor of 4 bits as input and 1 as output. I have tray several ways, using cases, if, etc. but I keep getting this error: WARNING:PhysDesignRules:367 - The signal <A<2>_IBUF> is incomplete. The signal does not drive any load pins in the design. WARNING:Par:288 - The signal A<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. And when I program in