volatile

原文链接： https://www.cnblogs.com/laowen-zjw/p/6735790.html 对于java开发工程师来说，并发编程一直是一个具有挑战性的技术，本章将给大家介绍一下volatile的原理。 下面介绍几个概念： 共享变量：共享变量是指可以同时被多个线程访问的变量，共享变量是被存放在堆里面，所有的方法内临时变量都不是共享变量。 重排序：重排序是指为了提高指令运行的性能，在编译时或者运行时对指令执行顺序进行调整的机制。重排序分为编译重排序和运行时重排序。编译重排序是指编译器在编译源代码的时候就对代码执行顺序进行分析，在遵循as-if-serial的原则前提下对源码的执行顺序进行调整。as-if-serial原则是指在单线程环境下，无论怎么重排序，代码的执行结果都是确定的。运行时重排序是指为了提高执行的运行速度，系统对机器的执行指令的执行顺序进行调整。 可见性：内存的可见性是指线程之间的可见性，一个线程的修改状态对另外一个线程是可见的，用通俗的话说，就是假如一个线程A修改一个共享变量flag之后，则线程B去读取，一定能读取到最新修改的flag。 说到这里，可能有些同学会觉得，这不是废话吗，线程A修改变量flag后，线程B肯定是可以拿到最新的值的呀。假如你真的这么认为，那么请运行一下以下的代码： package test; public class

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: Linux's synchronization primitives (spinlock, mutex, RCUs) use memory barrier instructions to force the memory access instructions from getting re-ordered. And this reordering can be done either by the CPU itself or by the compiler. Can someone show some examples of GCC produced code where such reordering is done ? I am interested mainly in x86. The reason I am asking this is to understand how GCC decides what instructions can be reordered. Different x86 mirco architectures (for ex: sandy bridge vs ivy bridge) use different cache

public void MyTest() { bool eventFinished = false; myEventRaiser.OnEvent += delegate { doStuff(); eventFinished = true; }; myEventRaiser.RaiseEventInSeperateThread() while(!eventFinished) Thread.Sleep(1); Assert.That(stuff); } Why can't eventFinished be volatile and does it matter? It would seem to me that in this case the compiler or runtime could become to smart for its own good and 'know' in the while loop that eventFinished can only be false. Especially when you consider the way a lifted variable gets generated as a member of a class and the delegate as a method of that same class and

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: What does AtomicBoolean do that a volatile boolean cannot achieve? 回答1: They are just totally different. Consider this example of a volatile integer: volatile int i = 0; void incIBy5() { i += 5; } If two threads call the function concurrently, i might be 5 afterwards, since the compiled code will be somewhat similar to this (except you cannot synchronize on int ): void incIBy5() { int temp; synchronized(i) { temp = i } synchronized(i) { i = temp + 5 } } If a variable is volatile, every atomic access to it is synchronized, but it is not

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: gcc fails to compile the code below, while clang compiles ok. I have no control on the macro PORTB , as it is in a 3rd party library ( avr ). Is it a gcc bug? How can I work around it in gcc ? As a workaround is somehow possible to create a pre-processor macro which extracts the numerical value from PORTB? Note this question is similar, but not identical to my previous question . It is also different from this question, where the developer has the flexibility to change the rhs of the assignment, thus avoiding the reinterpret_cast . #include

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: So I want an array with 10 volatile booleans, not a volatile array with 10 booleans. It probably does not even make sense to have a volatile array reference, correct me if I am wrong. 回答1: If it's only 10 and is always 10, you could simply write: private volatile boolean b1, b2, ..., b10; A possibly cleaner way would be to use an AtomicIntegerArray(10) and map between integers and booleans (0=false, 1=true). You should clarify the reason why you need 10 volatile booleans: there may be a better way. 回答2: I believe the only way is to have a

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 由 翻译 强力驱动 问题: Cache is controlled by cache hardware transparently to processor, so if we use volatile variables in C program, how is it guaranteed that my program reads data each time from the actual memory address specified but not cache. My understanding is that, Volatile keyword tells compiler that the variable references shouldn't be optimized and should be read as programmed in the code. Cache is controlled by cache hardware transparently, hence when processor issues an address, it doesn't know whether the data is coming from cache or the

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: I'm wondering why no compilers are prepared to merge consecutive writes of the same value to a single atomic variable, e.g.: #include std::atomic y(0); void f() { auto order = std::memory_order_relaxed; y.store(1, order); y.store(1, order); y.store(1, order); } Every compiler I've tried will issue the above write three times. What legitimate, race-free observer could see a difference between the above code and an optimized version with a single write (i.e. doesn't the 'as-if' rule apply)? If the variable had been volatile, then obviously no

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: From FreeRTOS.org , regarding Debugging Hard Fault & Other Exceptions on ARM Cortex-M3 and ARM Cortex-M4 microcontrollers , according to FreeRTOS guys we can use the following code in order to debug a ARM Cortex-M Hard Fault- /* The fault handler implementation calls a function called prvGetRegistersFromStack(). */ static void HardFault_Handler(void) { __asm volatile ( " tst lr, #4 \n" " ite eq \n" " mrseq r0, msp \n" " mrsne r0, psp \n" " ldr r1, [r0, #24] <======== NOTE THIS LINE \n" " ldr r2, handler2_address_const \n" " bx r2 \n" "

可以将文章内容翻译成中文,广告屏蔽插件可能会导致该功能失效(如失效，请关闭广告屏蔽插件后再试): 问题: I was looking at LazyInitializer.EnsureInitialized(ref T, Func{T}) in Reflector, and there appears to be a volatile local variable in that method volatile object local1 = s_barrier; . I can think of two possible reasons for this: .NET may get to use features that are not supported by a given language, or The actual code does not declare a volatile local variable, but when the compiled code is decompiled by Reflector, it looks like a volatile local variable. Does anyone know which is the case here (or whether there might be some other